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Secondary-Side Controller with Current Share and Housekeeping
ADM1041
PRODUCT FEATURES
Digital calibration via internal EEPROM Supports SSI specification Comprehensive fault detection Reduced component count on secondary side Standalone or microcontroller control
INTERFACE AND INTERNAL FEATURES
SMBus interface (I2C compatible) Low-drift precision 2.5 V reference Voltage error amplifier Differential current sense Sense resistor or current transformer option Overvoltage protection Undervoltage protection Overcurrent protection Overtemperature protection Start-up undervoltage blanking Programmable digital debounce and delays 352-byte EEPROM available for field data 160-byte EEPROM for calibration Ground continuity monitoring
SECONDARY-SIDE FEATURES
Generates error signal for primary-side PWM Output voltage adjustment and margining Current sharing Current limit adjustment OrFET control Programmable soft-start slew rate Standalone or microcontroller operation Differential load voltage sense AC mains undervoltage detection (ac sense) Overvoltage protection
APPLICATIONS
Network servers Web servers Power supply control
RS
OrFET VOUT
RLOAD
GND VDD VDD BIAS
PWM CONTROLLER VDD VDD
VDD
ADM1041
THERMISTOR FG CBD CS-/VLS FD SHRO CS+ SHRS VDD VS + VCMP VS- ICT PULSE AC_OK MON2 DC_OK PSON PEN ADD0 CCMP SCMP SCL SDA GND
SHARE BUS
VOUT VS + VS-
OTP VDD
MICROCONTROLLER OPTIONAL
ISOLATION BARRIER
Figure 1. Typical Application Circuit Rev. A
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04521-0-031
ADM1041 TABLE OF CONTENTS
Specifications..................................................................................... 6 Absolute Maximum Ratings.......................................................... 13 ESD Caution................................................................................ 13 Pin Configuration and Function Descriptions........................... 14 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 19 Power Management.................................................................... 19 Gain Trimming and Configuration ......................................... 19 Differential Remote Sense Amplifier............................................ 20 Set Load Voltage.......................................................................... 20 Load Overvoltage (OV) ............................................................. 20 Local Voltage Sense .................................................................... 20 Local OverVoltage Protection (OVP)...................................... 20 Local UnderVoltage Protection (UVP) ................................... 20 False UV Clamp.......................................................................... 20 Voltage Error Amplifier ............................................................. 21 Main Voltage Reference ............................................................. 21 Current Sense Amplifier............................................................ 21 Current Sensing .......................................................................... 22 Current Transformer Input ....................................................... 22 Current Sense Calibration......................................................... 22 Current Limit Error Amplifier.................................................. 22 Overcurrent Protection ............................................................. 22 Current Share .................................................................................. 24 Current Share Offset .................................................................. 24 ISHARE Drive Amplifier................................................................. 24 Differential Sense Amplifier...................................................... 24 ISHARE Error Amplifier................................................................. 24 ISHARE Clamp................................................................................. 24 Share_ok Detector ...................................................................... 24 Pulse/ACSENSE2................................................................................. 27 Pulse ............................................................................................. 27 ACSENSE.......................................................................................... 27 OrFET Gate Drive ...................................................................... 28 Oscillator and Timing Generators ............................................... 30 Logic I/O and Monitor Pins...................................................... 30 SMBus Serial Port....................................................................... 33 Microprocessor Support............................................................ 33 Broadcasting................................................................................ 34 SMBus Serial Interface............................................................... 34 General SMBus Timing ............................................................. 34 SMBus Protocols for RAM and EEPROM.............................. 36 SMBus Read Operations ........................................................... 38 SMBus Alert Response Address (ARA)................................... 39 Support for SMBus 1.1............................................................... 39 Layout Considerations............................................................... 39 Power-Up Auto-Configuration ................................................ 39 Extended SMBus Addressing.................................................... 40 Backdoor Access ......................................................................... 40 Register Listing ............................................................................... 41 Detailed Register Descriptions ..................................................... 42 Manufacturing Data................................................................... 51 Microprocessor Support ................................................................ 52 Trim Table........................................................................................ 54 Appendix A--Configuration Table .............................................. 55 Appendix B--Test Name Table..................................................... 61 Outline Dimensions ....................................................................... 64 Ordering Guide .......................................................................... 64
REVISION HISTORY 3/04-Revision Sp0: Initial Version 5/04-Changed from Rev. Sp0 to Rev. A
Rev. A | Page 2 of 64
ADM1041
GENERAL DESCRIPTION
The ADM1041 is a secondary-side and management IC specifically designed to minimize external component counts and to eliminate the need for manual calibration or adjustment on the secondary-side controller. The principle application of this IC is to provide voltage control, current share, and housekeeping functions for single output in N+1 server power supplies. The ADM1041 is manufactured with a 5 V CMOS process and combines digital and analog circuitry. An internal EEPROM provides added flexibility in the trimming of timing and voltage and selection of various functions. Programming is done via an SMBus serial port that also allows communication capability with a microprocessor or microcontroller. The usual configuration using this IC is on a one per output basis. Outputs from the IC can be wire-ORed together or bused in parallel and read by a microprocessor. A key feature on this IC is support for an OrFET circuit when higher efficiency or power density is required. are needed to maintain a stable output. To maintain a stable loop, the ADM1041 uses three main inputs: * * * Remote voltage sense Load current sense Current sharing information
In this example, a resistor divider senses the output current as a voltage drop across a sense resistor (RS) and feeds a portion into the ADM1041. Remote local voltage sense is monitored via VS+ and VS- pins. Finally, current sharing information is fed back via the share bus. These three elements are summed together to generate a control signal (VCMP), which closes the loop via an optocoupler to the primary side PWM controller. Another key feature of the ADM1041 is its control of an OrFET. The OrFET causes lower power dissipation across the ORing diode. The main function of the OrFET is to disconnect the power supply from the load in the event of a fault occurring during steady state operation, for example, if a filter capacitor or rectifier fails and causes a short. This eliminates the risk of bringing down the load voltage that is supplied by the redundant configuration of other power supplies. In the case of a short, a reverse voltage is generated across the OrFET. This reverse voltage is detected by the ADM1041 and the OrFET is shut down via the FG pin. This intervention prevents any interruption on the power supply bus. The ADM1041 can then be interrogated via the serial interface to determine why the power supply has shut down. This application circuit also demonstrates how temperature can be monitored within a power supply. A thermistor is connected between the VDD and MON2 pins. The thermistor's voltage varies with temperature. The MON2 input can be programmed to trip a flag at a voltage corresponding to an overheating power supply. The resulting action may be to turn on an additional cooling fan to help regulate the temperature within the power supply.
RSENSE LOAD
SAMPLE APPLICATION CIRCUIT DESCRIPTION
Figure 1 shows a sample application circuit using the ADM1041. The primary side is not detailed and the focus is on the secondary side of the power supply. The ADM1041 controls the output voltage from the power supply to the designed programmed value. This programmed value is determined during power supply design and is digitally adjusted via the serial interface. Digital adjustment of the current sense and current limit is also calibrated via the serial interface, as are all of the internal timing specifications. The control loop consists of a number of elements, notably the inputs to the loop and the output of the loop. The ADM1041 takes the loop inputs and determines what, if any, adjustments
PWM + PRIMARY DRIVER
OPTOCOUPLER
AC PULSE SENSE
DIFF CURRENT SENSE
OrFET CONTROL
ERROR AMP
CURRENT SHARE SOFT START DIFF LOAD AND LOCAL VOLTAGE SENSE
SHARE BUS
ADM1041
EEPROM AND RAM AND TRIM
SMBus
C
Figure 2. Application Block Diagram
Rev. A | Page 3 of 64
04521-0-002
VOLT, TEMP MONITOR AND FAULT DETECTION
(C OR STANDALONE OPERATION)
ADM1041
CURRENT SOURCE GATE DRAIN
VOUT
V = VOUT + 10V
3
2
6
0.525V PULSEOK PENOK CLK Q R OrFET OK POLARITY AC_OK SQ CLK Q R 1 mSec R VREF REVERSE VOLTAGE DETECTOR REVERSEOK 1 Sec R LOADVOK
CS+ CS-/FS /VLS FD
VDD FG
19
PULSE ACSENSE1 SQ
9
5.3k
SELECT ACSENSE
ACSENSE2
5.3k
10
1.5V
TRIM HYSTERESIS
AC SENSE ORFET CONTROL
VREF VDD REG 17h b7 CURRENT SHARE OFFSET (VSHARE, IOUT = 0) TO VOLTAGE ERROR AMP ISHARE ERROR AMPLIFIER SCMP
22
Figure 3. Chip Diagram, Part 1
Rev. A | Page 4 of 64
IRS/ ICT 9R SET CURRENT SHARE R 40k VREF SET CURRENT LIMIT LEVEL SHAREOK CURRENT LIMIT ERROR AMP SET GAIN
GAIN = 10
ISHARE CLAMP ISHARE DRIVE AMPLIFIER SHRO
24
TRANSFORMER CURRENT SENSE CONFIGURATON
12V SHARE BUS 60A DIFFERENTIAL SENSE
23
ICT
8
1N4148
R1
50k
SHRS+ R2
20
CURRENT TRANSFORMER
CCMP 50mV 50mV 50k 50k 50k
VS- /SHRS- GAIN = (R1 + R2)/R2 REMOTE -VE SENSE
4
CURRENT SENSE
CURRENT SHARE
04521-0-037
VS+
21
70A 35k CURRENT LIMIT 1V DIFF. VOLTAGE SENSE VCMP
5
REMOTE SENSE FROM LOAD 35k 3V
20
VS- 35k CURRENT SHARE 35k SET LOAD VOLTAGE 1.5V VREF SOFT START RAMP UP VOLTAGE ERROR AMP CAPTURE
SET LOAD OVERVOLTAGE LOADVOK x1.3 OCPF FALSE UV CLAMP VREF 1.25V
VLS
2
VOLTAGE ERROR AMP
SET UV CLAMP THRESHOLD
SET OVP THRESHOLD OVP 1.5V
UVP SET UVP THRESHOLD OCP 1.25V 2.5V
18
VOLTAGE SENSE
OCP
OTP/ MON5 MON5
VREF 18 1.25V 1.5V INTERNAL REFERENCE 2.5V OVP
10 9
Figure 4. Chip Diagram, Part 2
Rev. A | Page 5 of 64
MAIN BAND GAP 1.25V EXTREFOK PENOK AC_OK ORFETOK AUXILIARY REFERENCE 2.0V POR INTREFOK SHAREOK UVP PENOK AC_OK ORFETOK SHAREOK REFERENCE MONITOR RESET VDDOK 4.0V UVLLO S VDDOK R Q VDDOV 4.4V UVLHI PWRON 6.0V-6.5V OVP S 10s-20s 0.2V GNDOK GROUND MONITOR R Q Q VDDOV
CONFIGURE WRITE REGISTERS
VDD 1
MON1 MON1 MON2 MON2
16
MON3 GENERAL LOGIC MON3
17
NOTES:
1
HIGH VOLTAGE ANALOG I/O PIN
MON4 MON4 PSON CLOCK VREF AC_OK DC_OK CBD CONTROL REGISTERS PEN CONFIGURE I/Os
STATUS (READ REGISTERS) 13 16
XX
PSON
2
STANDARD I/0 PIN
18
VREF
18
AC_OK
17
XX
DC_OK
11
CBD/ALERT
12
3
ALL POTENTIOMETERS ( ARE DIGITALLY PROGRAMMBALE THROUGH REGISTERS
)
PEN
VS- 20
CONTROL LINES SERIAL INTERFACE
SCL PEN CS
14
SCL/ ACONLink SDA/ PSONLINK 15 ADD0
GND 7 gndok_dis
LOGIC AND GPIO POWER MANAGEMENT
ADM1041
04521-0-038
ADM1041 SPECIFICATIONS
TA = -40 to +85C, VDD = 5 V 10%, unless otherwise noted. Table 1.
Parameter SUPPLIES VDD IDD, Current Consumption Peak IDD, during EEPROM Erase Cycle1, 2 UNDERVOLTAGE LOCKOUT, VDD Start-Up Threshold Stop Threshold Hysteresis VREF, 2.5 VREFOUT Output Voltage Line Regulation Load Regulation Temperature Stability2 Long-Term Stability2 Current Limit Output Resistance2 Load Capacitance Ripple Due to Autozero2 POWER BLOCK PROTECTION VDD Overvoltage VDD Overvoltage Debounce VREF Overvoltage VREFOUT Undervoltage Open Ground Debounce POWER-ON RESET DC Level DIFFERENTIAL LOAD VOLTAGE SENSE INPUT, (VS-, VS+) VS- Input Voltage VS+ Input Voltage VS- Input Resistance VS+ Input Resistance VNOM Adjustment Range Set Load Voltage Trim Step Min 4.5 Typ 5.0 6 Max 5.5 10 40 4.5 4.2 Unit V mA mA See Figure 9. 4 3.7 4.3 4 0.3 2.50 0 0 100 5 10 0.5 1 5 6.2 2.9 2.1 0.2 V V V V mV mV ppm/C mV mA nF mV p-p V s V V V s V Reg 0Fh[4:2] = 111. See Table 24. IREF = 1 mA, TA = 25C 4.5 V VDD 5.5 V 0 mA IREF 2 mA IREF = 1 mA Over 1,000 hr, TJ = 125C VREF = 2.4 V Recommended for stability VREF refreshed at 30 kHz Test Conditions/Comments
2.49 -5 -5
2.51 +5 +5
20
5.8 10
6.5 20
0.1 100 1.5
0.35 200 2.75
Latching Internal External VGND positive with respect to VS- VDDOK VDD rising See Figure 6. VNOM = (VS+ - VS-) VNOM is typically 2 V Voltage on Pin 20 Voltage on Pin 21
2.2
0.5 VDD - 2 35 500 1.7 to 2.3 0.10 to 0.14 1.74 -> 3.18 105 to 120 0.09 1.6 100 200 300 400 2
V V k k V % mV % % mV s s s s s
Set Load Overvoltage Trim Range Set Load Overvoltage Trim Step
Recover from Load OV False to FG True
1.7 V VNOM 2.3 V typ 8 bits, 255 steps Reg 19h[7:0]. See Table 34 1.7 V VNOM 2.3 V min 8 bits, 255 step/s Reg 08h[7:0]. See Table 17. VS+ = 2.24 V Reg 03h[1:0] = 00. See Table 12. Reg 03h[1:0] = 01. See Table 12. Reg 03h[1:0] = 10. See Table 12. Reg 03h[1:0] = 11. See Table 12.
Operate Time from Load OV to FG False
Rev. A | Page 6 of 64
ADM1041
Parameter LOCAL VOLTAGE SENSE, VLS, AND FALSE UV CLAMP Input Voltage Range3 Stage Gain False UV Clamp, VLS, Input Voltage Nominal, and Trim Range Clamp Trim Step Clamp Trim Step Local Overvoltage Nominal and Trim Range OV Trim Step OV Trim Step Noise Filter, for OVP Function Only Local Undervoltage Nominal and Trim Range UV Trim Step UV Trim Step Noise Filter, for UVP Function Only VOLTAGE ERROR AMPLIFIER, VCMP Reference Voltage VREF_SOFT_START Temperature Stability2 Long-Term Voltage Stability2 Soft-start Period Range Set Soft-start Period Min Typ Max Unit Test Conditions/Comments See Figure 9. Set by external resistor divider. At VLS = 1.8 V
1.3
2.3 1.3 1.85 0.2 3.1
VDD-2 2.1
V V % mV
VRANGE 8 bits, 255 steps, Reg 18h[7:0]. See Table 33.
1.9
2.4 0.15 3.7
2.85
V % mV VRANGE 8 bits, 255 steps Reg 0Ah[7:0]. See Table 33.
5 1.3
1.7 0.18 3.1
25 2.1
s V % mV VRANGE 8 bits, 255 steps, Reg 09h[7:0]. See Table 18. See Figure 14. TA = 25C -40C TA 85C Over 1,000 hr, TJ = 125C Ramp is 7 bit, 127 steps Reg 10h[3:2] = 00. See Table 25. Reg 10h[3:2] = 01. See Table 25. Reg 10h[3:2] = 10. See Table 25. Reg 10h[3:2] = 11. See Table 25. See Figure 11. At IVCMP = 180 A At VVCMP > 1 V At VVCMP < VDD - 1 V Reg 17h[7] = 0. See Table 18. ISENSE mode. See Figure 13. Set by external divider Reg 16h[5:3] = 000. See Table 31. Reg 16h[5:3] = 001. See Table 31. Reg 16h[5:3] = 010. See Table 31. Reg 16h[5:3] = 100. See Table 31. Reg 16h[5:3] = 101. See Table 31. Reg 16h[5:3] = 110. See Table 31. VCM = 2.0 V 8 bits, 255 steps Reg 14h[7:0]. See Table 29.
300 1.49 100 0.2 0 300 10 20 40 1 2.7
600 1.51
s V V/C % ms s ms ms ms MHz mA/V A A
40
Unity Gain Bandwidth, GBW Transconductance Source Current Sink Current DIFFERENTIAL CURRENT SENSE INPUT, CS-, CS+ Common-Mode Range External Divider Tolerance Trim Range (with respect to input)
1.9 250 250
3.5
0 -5 -10 -20 5 10 20 20 39 78
VDD-2
V mV mV mV mV mV mV V V V
External Divider Tolerance Trim Step Size (with respect to input)
Rev. A | Page 7 of 64
ADM1041
Parameter DC Offset Trim Range (with respect to input) Min Typ -8 -15 -30 8 15 30 30 50 120 Max Unit mV mV mV mV mV mV V V V Test Conditions/Comments Reg 17h[2:0] = 000. See Table 32 . Reg 17h[2:0] = 001. See Table 32. Reg 17h[2:0] = 010. See Table 32. Reg 17h[2:0] = 100. See Table 32. Reg 17h[2:0] = 101. See Table 32. Reg 17h[2:0] = 110. See Table 32. VCM = 2.0 V, VDIFF = 0 V 8 bits, 255 steps Reg 15h[7:0]. See Table 30. VCSCM = 2.0V, 0C TA 85 OC SHRS = SHRO = 2 V. Gain = 230x 3 6 Gain Range (ISENSE) Gain Setting 1 (Reg 16h[2:0] = 000) Gain Setting 2 (Reg 16h[2:0] = 001) Gain Setting 3 (Reg 16h[2:0] = 010) Gain Setting 4 (Reg 16h[2:0] = 100) Gain Setting 5 (Reg 16h[2:0] = 101) Gain Setting 6 (Reg 16h[2:0] = 110) Full Scale (No Offset) Attenuation Range Current Share Trim Step (at SHRO) Gain Accuracy2, 4, 40 mV at CS+, CS- Gain Accuracy2, 4, 20 mV at CS+, CS- Gain Accuracy2, 4, 40 mV at CS+, CS- SHARE BUS OFFSET Current Share Offset Range Zero Current Offset Trim Step 0.4 5.5 CURRENT TRANSFORMER SENSE INPUT, ICT Gain Setting 0 Gain Setting 1 4.5 2.57 V/V V/V % mV -5 -5 -2.5 1 0.5 65 85 110 135 175 230 2.0 65 to 99 0.4 8 +5 +5 +2.5 % % V/V V/V V/V V/V V/V V/V V % % mV % % % Chopper ON Chopper OFF Input voltage range at CS+, CS- 34.0 mV - 44.5 mV. Gain = 65x 26.0 mV - 34.0 mV. Gain = 85x 20.0 mV - 26.0 mV. Gain = 110x 16.0 mV - 20.0 mV. Gain = 135x 12.0 mV - 16.0 mV. Gain = 175x 9.5 mV - 12.0 mV. Gain = 230x VZO = 0 Reg 06h[7:1]. See Table 15. SHRS = SHRO = 1 V 7 bits, 127 steps ISHARE slope 0 V VCSCM 0.3 V. Gain = 65x VCSCM = Input Common Mode VCSCM = 2.0V, 0C TA 85C Gain = 135x VCSCM = 2.0 V, 0C TA 85C Gain = 65x See Figure 13. Reg 17h[7] = 1. See Table 32. Reg 17h[5] = 1. See Table 32. 0 VTRIM 1.25 V 8 bits, 255 steps, VCT = 1.0 V Reg 05h[7:0]. See Table 14. Reg 17h[7] = 1. See Table 32. Reg 06h = FEh. See Table 15. Reg 17h[5] = 0, VSHARE = 2 V. Table 31 Reg 17h[5] = 1. See Table 32. Reg 15h = 05h, approx 1 A. See Table 30. VSHARE = 2 V. Gain setting = 4.5 Gain setting = 2.57 See Current Transformer Input Section. 15 steps Reg 15h[3:0]. See Table 30. See Figure 38. See Absolute Maximum Ratings.
DC Offset Trim Step Size (with respect to input) CURRENT SENSE CALIBRATION Total Current Sense Error2 (Gain and Offset)
1.25
V
CT Input Sensitivity CT Input Sensitivity Input Impedance2 Source Current Source Current Step Size Reverse Current for Extended SMBus Addressing (Source Current) 5
0.45 0.79 20
0.5 1.0 50 2.0 170
0.68 1.20
V V k A nA
3.5
5
7
mA
Rev. A | Page 8 of 64
ADM1041
Parameter CURRENT LIMIT ERROR AMPLIFIER Current Limit Trim Range2 Current Limit Trim Step Current Limit Trim Step Transconductance Output Source Current Output Sink Current CURRENT SHARE DRIVER Output Voltage6 Short Circuit Source Current Source Current Sink Current CURRENT SHARE DIFFERENTIAL SENSE AMPLIFIER VS- Input Voltage VSHRS Input Voltage Input Impedance2 Gain CURRENT SHARE ERROR AMPLIFIER Transconductance, SHRS to SCMP Output Source Current Output Sink Current Input Offset Voltage Share OK Window Comparator Threshold (Share Drive Error) Min 105 1.1 26.5 100 200 40 40 300 Typ Max 130 Unit % % mV A/V A A V mA mA A Test Conditions/Comments See Figure 13 After ISHARE calibration 2.0 VSHARE 2.8 V typ. 5 bits, 31 steps. Reg 04h[7:3]. See Table 13. ICCMP = 20 A. See Figure 12. VCCMP = > 1 V VCCMP = < VDD - 1 V See Figure 14. RL = 1 k, VSHRS VDD - 2 V Current at which VOUT does not drop by more than 5% VSHARE = 2.0 V See Figure 14. Voltage on Pin 20 Voltage on Pin 23 VSHRS = 0.5 V, VS- = 0.5 V
VDD - 0.4 55 15 60 100
0.5 VDD - 2 65 100 1.0 200 40 40 50 300
V V k V/V A/V A A mV
100
40
60
ISCMP = 20 A VSCMP > 1 V VSCMP < VDD - 1 V Master/slave arbitration SHRS = 2 V SHRTHRESH Reg 04h[1:0] = 00. See Table 13. Reg 04h[1:0] = 01. See Table 13. Reg 04h[1:0] = 10. See Table 13. Reg 04h[1:0] = 11. See Table 13. Figure 10. VCCMP = 0.7 V, VS+ = 1.5 V VS+ = 0 V, VSCMP = 0 V VSCMP = 3.5 V. Reg 10h[5:4] = 00. See Table 25. Reg 10h[5:4] = 01. See Table 25. Reg 10h[5:4] = 10. See Table 25. Reg 10h[5:4] = 11. See Table 25. Open-drain N-channel FET IIO = 5 mA IIO = 10 mA VCS- = FS Voltage set by CS resistor divider Voltage on CS- pin. TA = 25C.
100 200 300 400
mV mV mV mV
CURRENT LIMIT Current Limit Control Lower Threshold Current Limit Control Upper Threshold CURRENT SHARE CAPTURE Current Share Capture Range 1.3 3.5 0.7 1.4 2.1 2.8 0.6 1 2 3 4 1.0 1.3 2.6 3.9 5.2 1.4 0.4 0.8 +5 2.0 VDD - 2 V V % % % % V V V A V
Capture Threshold FET OR GATE DRIVE Output Low Level (On) Output Leakage Current REVERSE VOLTAGE COMPARATOR, FS, FD Common-Mode Range
-5 0.25
Rev. A | Page 9 of 64
ADM1041
Parameter Reverse Voltage Detector Turn-Off Threshold Min Typ 100 150 200 250 Reverse Voltage Detector Turn-On Threshold 20 30 40 50 FD Input Impedance FS Input Impedance ACSENSE1/ACSENSE2 COMPARATOR (AC or Bulk Sense) Threshold Voltage Threshold Adjust Range Threshold Trim Step 1.25 1.10 0.8 10 200-550 50 0.6 1 0.525 1 1 1.2 1.40 V V % mV mV mV ms V s s % V s s s s ms 500 20 mV mV mV mV k k Max Unit mV mV mV mV Test Conditions/Comments VCS- = 2 V for threshold specs Reg 03h[7:6] = 00. See Table 12. Reg 03h[7:6] = 01. See Table 12. Reg 03h[7:6] = 10. See Table 12. Reg 03h[7:6] = 11. See Table 12. VCS- = 2 V for threshold specs Reg 03h[5:4] = 00. See Table 12. Reg 03h[5:4] = 01. See Table 12. Reg 03h[5:4] = 10. See Table 12. Reg 03h[5:4] = 11. See Table 12.
Reg 12h[2] = 0 Reg 0Dh[3:2] = 00. See Table 22 . Reg 12h[2] = 1 Reg 0Eh[7:6] = 00. See Table 23. Min: DAC = 0 Max: DAC = Full Scale 1.10 VTRIM 1.4 V 5 bits, 31 steps Reg 0Ch[7:3]. See Table 21. VACSENSE > 1 V, RTHEVENIN = 909R 200 VTRIM 550 mV. 7 steps Reg 0Ch[2:0]. See Table 21.
Hysteresis Adjust Range Hysteresis Trim Step Noise Filter PULSE-IN Threshold Voltage PULSE_OK On Delay PULSE_OK Off Delay OSCILLATOR OCP OCP Threshold Voltage2 OCP Shutdown Delay Time (Continuous Period in Current Limit)
0.8 -5 0.3
1.2 +5 0.7
Unless otherwise specified Force CCMP for drop in VCMP Reg 11h[2] = 0. See Table 26. Reg 12h[4:3] = 00. See Table 27. Reg 12h[4:3] = 01. See Table 27. Reg 12h[4:3] = 10. See Table 27. Reg 12h[4:3] = 11. See Table 27. Reg 11h[2] = 1. See Table 26. VCCMP = 1.5 V
0.5 1 2 3 4
OCP Fast Shutdown Delay Time MON1, MON2, MON3, MON4 Sense Voltage Hysteresis OVP Noise Filter UVP Noise Filter OTP (MON5) Sense Voltage Range OTP Trim Step
0
100
1.21 5 300 2.2
1.25 0.1
1.29 25 600 2.45
V V s s Reg 0Fh[4:2] = 01x or 10x. Table 24. V mV
24
Hysteresis
100
130
160
A
2.1 VTRIM 2.45 V 4 bits, 15 steps, Reg 0Bh[7:4]. See Table 20. VOTP = 2 V
Rev. A | Page 10 of 64
ADM1041
Parameter OVP Noise Filter UVP Noise Filter PSON7 Input Low Level8 Input High Level8 Debounce Min 5 300 Typ Max 25 600 Unit s s Test Conditions/Comments Reg 0Fh[4:2] = 010 or 100. See Table 24. Reg 0Fh[4:2] = 011 or 101. See Table 24. Reg 0Eh[4:2] = 00x. See Table 23.
0.8 2.0 80 0 40 160
V V ms ms ms ms
Reg 0Fh[1:0] = 00. See Table 24. Reg 0Fh[1:0] = 01. See Table 24. Reg 0Fh[1:0] = 10. See Table 24. Reg 0Fh[1:0] = 11. See Table 24.
PEN7, DC_OK7, CBD, AC_OK Open-Drain N-Channel Option Output Low Level = On8 Open-Drain P-Channel Output High Level = On8 Leakage Current DC_OK7 DC_OK, On Delay (Power-On and OK Delay)
0.4 2.4 -5 400 200 800 1600 2 0 1 4 0.8 2.2 100 -5 0.4 350 +5 0.4 VDD/2 VDD - 0.5 400 50 4.7 4.7 4 4.7 4 1000 300 250 300 100 100 250
V V A ms ms ms ms ms ms ms ms V V V A A V V V kHz ns s s s s s ns ns ns ns k cycles Years
ISINK = 4 mA VOH_PEN ISOURCE = 4 mA Reg 0Fh[7:5] = 00x. See Table 24. Reg 0Eh[1:0] = 00. See Table 23. Reg 0Eh[1:0] = 01.See Table 23. Reg 0Eh[1:0] = 10. See Table 23. Reg 0Eh[1:0] = 11. See Table 23. Reg 10h[7:6] = 00. See Table 25. Reg 10h[7:6] = 01. See Table 25. Reg 10h[7:6] = 10. See Table 25. Reg 10h[7:6] = 11. See Table 25.
+5
DC_OK, Off Delay (Power-Off Early Warning)
SMBus, SDL/SCL Input Voltage Low8 Input Voltage High8 Output Voltage Low8 Pull-Up Current Leakage Current ADD0, HARDWIRED ADDRESS BIT ADD0 Low Level8 ADD0 Floating ADD0 High8 SERIAL BUS TIMING Clock Frequency Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU;STA Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Data Setup Time, tSU;DAT Data Hold Time, tHD;DAT EEPROM RELIABILITY Endurance9 Data Retention10
VDD = 5 V, ISINK = 4 mA
Floating See Figure 5.
Rev. A | Page 11 of 64
ADM1041
1
This specification is a measure of IDD during an EEPROM page erase cycle. The current is a dynamic. Refer to Figure 29 for a typical IDD plot during an EEPROM page erase. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Four external divider resistors are the same ration, which is selected to produce 2.0 V nominal at Pin 21 while at zero load current. Recommended values are 3.3 V 680R 1K 5.0 V 1K.5 1K 12 V 5K1 1K
RTOP RBOTTOM
4 5
Chopper off. The maximum specification here is the maximum source current of Pin 8 as specified by the Absolute Maximum Ratings. 6 All internal amplifiers accept inputs with common range from GND to VDD - 2 V. The output is rail to rail but the input is limited to GND to VDD - 2 V. See Figure 6. 7 These pins can be configured as open-drain N-channel or P-channel, (except PSON) and as normal or inverted logic polarity. Refer to Table 45. 8 A logic true or false is defined strictly according to the signal name. Low and high refer to the pin or signal voltages. 9 Endurance is qualified to 100,000 cycles as per JEDEC std. 22 method A117, and measured at -40C, +25C, and +85C. Typical endurance at 25C is 250,000 cycles. 10 Retention lifetime equivalent at junction temperature (TJ) = 55C as per JEDEC std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V. Derates with junction temperature.
tLOW
SCL
tR
tF
tHD:STA
tHD:STA
SDA
tHD:DAT
tHIGH tSU:DAT
tSU:STA
tSU:STO
tBUF
P S S P
Figure 5. Serial Bus Timing Diagram
SHRO
VA R1
VA = VDD - 0.4V
SHRS+ SHRS-
VB R1
VB = VDD - 2V R1 + R2 1k
04521-0-004
Figure 6. Amplifier Inputs and Outputs
Rev. A | Page 12 of 64
04521-0-005
ADM1041 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage (Continuous), VDD Data Pins SDA, SCL, VDATA Continuous Power at 25C, PD-QSOP24 Operating Temperature, TAMB Junction Temperature, TJ Storage Temperature, TSTG Lead Temperature (Soldering, 10 Seconds), TL ESD Protection on All Pins, VESD Thermal Resistance, Junction to Air, JA ICT Source Current1
1
Thermal Characteristics
Rating 6.5 V VDD + 0.5 V, GND - 0.3 V 450 mW -40C to +85C 150C -60C to +150C 300C 2 kV 150C/W 7 mA
24-Lead QSOP Package: JA = 150C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
This is the maximum current that can be sourced out from Pin 8 (ICT pin).
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 13 of 64
ADM1041 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1 VLS/CS-/FS 2 CS+ 3 CCMP 4 VCMP 5 FD 6
24 23 22 21 20
SHRO SHRS+ SCMP VS+ VS-/SHRS-
GND 7
19 FG TOP VIEW 18 VREF/AC_OK/OTP/MON5 (Not to Scale) 17 DC_OK/MON4 ICT 8 16 15 14 13
ADM1041
PULSE/ACSENSE1/MON1 9 ACSENSE2/MON2 10 CBD/ALERT 11 PEN 12
PSON/MON3 ADD0 SDA/PSONLINK SCL/AC_OKLink
04521-0-030
Figure 7. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 Mnemonic VDD VLS/CS-/FS Description Positive Supply for the ASIC. Normal range is 4.5 V to 5.5 V. Absolute maximum rating is 6.5 V. Inverting Differential Current Sense Input, Local Voltage Sense Pin, and OrFET Source. These three functions are served by a common divider. The local voltage sense input is used for local overvoltage and undervoltage sensing. This pin also provides an input to the false UV clamp that prevents shutdown during an external load overvoltage condition. When supporting an OrFET circuit, this pin represents the FET source and is the inverting input of a differential amplifier looking for the presence of a reverse voltage across the FET, which might indicate a failure mode. Noninverting Differential Current Sense Input. The differential sensitivity of CS+ and CS- is normally around 10 mV to 40 mV at the input to the ASIC. Nulling any external divider offset is achieved by injecting a trimmable amount of current into either the inverting or noninverting input of the second stage of the current sense amplifier. A compensation circuit is used to ensure the amount of current for zero-offset tracks the common-mode voltage. Nulling of any amplifier offset is done in a similar manner except that it does not track the common-mode voltage. Current Error Amplifier Compensation. This pin is the output of the current limit transconductance error amplifier. A series resistor and a capacitor to ground are required for loop compensation. Voltage Error Amplifier Compensation. This is the output of a voltage error transconductance amplifier. Compensate with a series capacitor and resistor to ground. An external emitter-follower or buffer is typically used to drive an optocoupler. Output voltage positioning may be obtained by placing a second resistor directly to ground. Refer to Analog Devices applications notes on voltage positioning. A divider from the OrFET drain is connected here. A differential amplifier is then used to detect the presence of a reverse voltage across the FET, which indicates a fault condition and causes the OrFET gate to be pulled low. Ground. This pin is double bonded for extra reliability. If the ground pin goes positive with respect to the remote sense return (VS-) for a sustained period indicating that the negative remote sense line is disconnected, PEN will be disabled. Input for Current Transformer. The sensitivity of this pin is suitable for the typical 0.5 V to 1 V signal that is normally available. If this function is enabled, the CS+ amplifier is disabled. This pin is also used for extended SMBus addressing, i.e., pulled below ground to allow additional SMBus addresses. Pulse Present, AC/Bulk Sense 1, or Monitor 1 Input. PULSE: This tells the OrFET circuit that the voltage from the power transformer is normal. A peak hold allows the OrFET circuit to pass through the pulse skipping that occurs with very light loads but turns off the circuit about one second after the last pulse is recognized. ACSENSE1: This sense function also uses the peak voltage on this pin to measure the bulk capacitor voltage. If too low, AC_OK and DC_OK can warn of an imminent loss of power. Threshold level and hysteresis can be trimmed. When not selected, ACSENSE1 defaults to true. MON1: When MON1 is selected for this pin, its input is compared against a 1.25 V comparator that could be used for monitoring a post regulated output; includes overvoltage, undervoltage, and overtemperature conditions.
Rev. A | Page 14 of 64
3
CS+
4 5
CCMP VCMP
6
FD
7
GND
8
ICT
9
PULSE/ACSENSE1/MON1
ADM1041
Pin No. 10 Mnemonic ACSENSE2/MON2 Description AC/Bulk Sense Input 2 or Monitor 2 Input. ACSENSE2: This alternative ACSENSE input can be used when the ACSENSE source must be different from that used for the OrFET. It also allows dc and opto-coupled signals that are not suitable for the OrFET control. MON2: When MON2 is selected for this pin, its input is compared against a 1.25 V comparator that could be used for monitoring a post regulated output; includes overvoltage, undervoltage, and overtemperature conditions. CBD: The crowbar drive pin allows implementation of a fast shutdown in case of a load overvoltage fault. The pin can be configured as an open-drain N-channel or P-channel and is suitable for driving a sensitive gate SCR crowbar. An external transistor is required if a high gate current is needed. Either polarity may be selected. ALERT: This pin can be configured to provide an ALERT function in microprocessor-supported applications whereby any of several ICs in a redundant system that detects a problem can interrupt and shut down the power supply. An alternative use is as a general-purpose logic output signal. Power Enable. This pin can be configured as an open-drain N-channel or P-channel that typically drives the PEN optocoupler. Providing that the PSON pin has been asserted to turn the output on, and that there are no faults, this pin drives an optocoupler on enabling the primary PWM circuit. Either polarity may be selected. SCL: SMBus Serial Clock Input. AC_OKLink: In non-microprocessor applications, this pin can be programmed to give the status of ACSENSE to all the ICs on the same bus. The main effect is to turn on undervoltage blanking whenever the sense circuit monitoring ac or bulk dc detects a low voltage. SDA: SMBus Serial Data Input and Output. PSONLINK: In non-microprocessor applications, this pin can be programmed to provide the PSON status to other ICs. This allows just one IC to be the PSON interface to the host system, or the PSONLINK itself can be the PSON interface. Chip Address Pin. There are three addresses possible using this pin, which are achieved by tying ADD0 to ground, tying to VDD, or being left to float. One address bit is available via programming at the device/daughter card level so the total number of addressable ICs can be increased to six. PSON: In non-microprocessor configurations, this is power supply on. As a standard I/O, this pin is rugged enough for direct interface with a customer's system. Either polarity may be selected. MON3: When MON3 is selected for this pin, its input is compared against a 1.25 V comparator that could be used for monitoring a post-regulated output; includes overvoltage, undervoltage, and overtemperature conditions. DC_OK: This pin is the output of a general-purpose digital I/O that can be configured as open-drain N-channel or open-drain P-channel suitable for wire-ORing with other ICs and direct interfacing with a customer's system. Either polarity may be selected. MON4: When MON4 is selected for this pin, its input is compared against a 1.25 V comparator that could be used for overtemperature protection and for monitoring a post-regulated output; includes overvoltage, undervoltage, and overtemperature conditions. Voltage Reference, Buffered Output, Overtemperature Protection, or Monitor 5. VREF: This is a 2.5 V precision reference voltage capable of sourcing 2 mA. This function is continuously monitored, and if the voltage falls below 2.0 V, PEN is disabled. Forcing this pin's voltage does not affect the integrity of the internal reference. AC_OK: This option can be configured as N-channel or P-channel and as normal or inverted polarity. At system level, a true AC_OK is used to indicate that the primary bulk voltage is high enough to support the system, and when false, that dc output is about to fail. MON5: A further option is to configure this as an analog input, MON5, with a flexible hysteresis and trimmable 2.5 V reference that makes this pin particularly suitable for overtemperature protection (OTP) sensing. Since hysteresis uses a switched 100 A current source, hysteresis can be adjusted via the source impedance of the external circuit. It can also be used for overvoltage and undervoltage functions. FET Gate Enable. When supporting an OrFET circuit, this is the gate drive pin. Since the open-drain voltage on the chip is limited to VDD, an external level shifter is required to drive the higher gate voltages suitable for the OrFET. This pin is configured as an open-drain N-channel. Either output polarity, low = on or low = off, may be selected. This pin is used as the ground input reference for the current share and load voltage sense circuits. It should be tied to ground at the common remote sense location. The input impedance is about 35 k to ground.
Rev. A | Page 15 of 64
11
CBD/ALERT
12
PEN
13
SCL/AC_OKLink
14
SDA/PSONLINK
15
ADD0
16
PSON/MON3
17
DC_OK/MON4
18
VREF/AC_OK/OTP/MON5
19
FG
20
VS-/SHRS-
ADM1041
Pin No. 21 Mnemonic VS+ Description This pin is the positive remote load voltage sense input and is normally divided down from the power supply output voltage to 2.0 V at no load using an external voltage divider. The input impedance is high. Output of the Current Share Transconductance Error Amplifier. Compensation is a series capacitor and resistor to ground. While VDD is normal and PEN is false, this pin is clamped to ground. When the converter is enabled (PEN true) and the clamp is released, the compensation capacitor charges providing a slow walk-in. The error amplifier input has a built-in bias so that all slaves in a parallel supply system do not compete with the master for control of the share bus. Current Share Sense. This is the noninverting input of a differential sense amplifier looking at the voltage on the share bus. For testing purposes, this pin is normally connected to SHRO. Calibration always expects this pin to be at 2.0 V with respect to SHRS-/VS-. If a higher share voltage is required, a resistor divider from SHRO or an additional gain stage, as shown in the application notes, must be used. Current Share Output. This output is capable of driving the share bus of several power supplies between 0 V and VDD - 0.4 V (10 k bus pull-down in each supply). Where a higher share bus voltage is required, an external amplifier is necessary. The current share output from the supply which, when bused with the share output of other power supplies working in parallel, allows each of the supplies to contribute essentially equal currents to the load.
22
SCMP
23
SHRS+
24
SHRO
Table 4. Default Pin States during EEPROM Download
Pin No. 11 12 17 18 19 Mnemonic CBD PEN DC_OK AC_OK FG State High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms). This pin is reconfigured at the end of the EEPROM download. High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms). This pin is reconfigured at the end of the EEPROM download. Active low (low if DC_OK true) at power-up. This pin is reconfigured during the EEPROM download. Active low (low if DC_OK true) at power-up. This pin is reconfigured during the EEPROM download. High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms). This pin is reconfigured at the end of the EEPROM download.
Rev. A | Page 16 of 64
ADM1041 TERMINOLOGY
Table 5.
Mnemonic POR UVL CVMode CCMode UVP Description Power-On Reset. When VDD is initially applied to the ASIC, the POR function clears all latches and puts the logic into a state that allows a clean start-up. Undervoltage Lockout. This is used on VDD to prevent spurious modes of operation that might occur if VDD is below a specific voltage. Constant Voltage Mode. This is the normal mode of operation of the power supply main output. The output voltage remains constant over the whole range of current specified. Constant Current Mode. This mode of operation occurs when the output is overloaded until or unless a shutdown event is triggered. The output current control level remains constant down to 0 V. Undervoltage Protection. If the output being monitored is detected as going under voltage, the UVP function sends a fault signal. After a delay, PEN goes false, the output is disabled, and either latch-off or an auto-restart occurs, depending on the mode selected. The DC_OK output also goes false immediately to show that the output is out of tolerance. Overvoltage Protection. If the output being monitored is detected as going over voltage, the OVP function latches and sends a fault signal, PEN goes false, and CBD goes true. The DC_OK output also goes false immediately. OVP faults are always latching and require the cycling of PSON or VDD or SMBus command to reset the latch. Overcurrent Protection. If the output being monitored is detected as going over current for a certain time, the OCP function sends out a fault signal that triggers a shutdown that can be latched or allowed to auto-restart, depending on the mode selected. Prior to shutting down, the DC_OK output goes false warning the system that output will be lost. The latch is the same one used for OVP. For auto-restart, the OCP time out period is configurable. Overtemperature Protection. If the temperature being sensed is detected as going over the selected limit, the OTP function sends out a fault signal that triggers a shutdown that can be latched or allowed to auto-restart depending on the mode selected. Prior to shutting down, the DC_OK output goes false warning the system that output will be lost. The latch is the same one used for OVP. Undervoltage Blanking. The UVP function is blanked (disabled) during power-up or if the ACSENSE function is false (ac line voltage is low). When in constant current mode, UVB is disabled. The status of ACSENSE must be known to the IC, either by virtue of the on-board ACSENSE or communicated by the SMBus with the help of an external microprocessor or by using AC_OKLink. When in constant current mode, due to an overload, UVB is applied for the overcurrent ride through period. The DC_OK function advises the system on the status of the power supply. When it is false, the system is assured of at least 1 ms of operation if ac power is lost for any reason. Other turn-off modes provide more warning time. This pin is an open-drain output. It can be configured as a P-channel pull-up or an N-channel pull-down. It may also be configured as positive or negative (inverted) logic. The AC_OK function advises the system whether or not sufficient bulk voltage is present to allow reliable operation. The system may choose to shut down if this pin is false. The power supply normally tries to maintain normal operation as long as possible, although DC_OK goes false when only a millisecond or so of operation time is left. This pin is an open-drain output. It can be configured as a P-channel pull-up or an N-channel pull-down. It may also be configured as positive or negative (inverted) logic. The DC_OK output is kept false for typically 100 ms to 900 ms during power-up. When the system is to be shut down in response to PSON going low, or in response to an OCP or OTP event, a signal is first sent to the DC_OK output to go false as a warning that power is about to be lost. PEN is signaled false typically 2 ms later (configurable). All of the inputs to the logic core are first debounced or digitally filtered to improve noise immunity. The debounce period for OV events is in the order of 16 s, for UV events it is 450 s, and for PSON it is typically 80 ms (configurable). A voltage from the secondary of the power transformer, which can provide an analog of the bulk supply, is rectified and lightly filtered and measured by the ac sense function. At start-up, if this voltage is adequate, this function signals the end user system that it is okay to start. If a brown-out occurs or ac power is removed, this function can provide early warning that power is about to be lost and allow the system to shut down in an orderly manner. While ACSENSE is low, UVB is enabled, which means undervoltage protection is not initiated. If ac power is so low that the converter cannot continue to operate, other protection circuits on the primary side normally shut down the converter. When an adequate voltage level is resumed, a power-up cycle is initiated.
OVP
OCP
OTP
UVB
DC_OK
AC_OK
DC_OKondelay DC_OKoffdelay
Debounce Digital Noise Filter
ACSENSE1
Rev. A | Page 17 of 64
ADM1041
Mnemonic Pulse_OK Description As well as providing ac sense, the preceding connection to the transformer is used to gate the operation of the OrFET circuit. If the output of the transformer is good and has no problems, the OrFET circuit allows gate drive to the OrFET. AC Sense Hysteresis. Configurable voltage on the ac sense input allows the ac sense upper and lower threshold to be adjusted to suit different amounts of low frequency ripple present on the bulk capacitor. An alternate form of ac sense can be accepted by the ASIC. This may in the form of an opto-coupled signal from the primary side where the actual level sensing might be done. As with the above, while ac is low and UVB is disabled, AC_OK is false and DC_OK is true. Any brownout protection that might be required on the primary is done on the primary side. At start-up, the voltage reference to the voltage error amplifier is brought up slowly in approximately 127 steps to provide a controlled rate of rise of the output voltage. An OVP fault on the auxiliary supply to the ASIC causes a standard OVP operation (see the OVP function). A UVL fault on the auxiliary supply to the IC causes a standard UVP operation (see the UVP function). In this mode, the housekeeping circuit attempts to restart the supply after an undervoltage event at about 1 second intervals. No other fault can initiate auto-restart. The internal precision reference is monitored by a separate reference for overvoltage and allows truly redundant OVP. The externally available reference is also monitored for an undervoltage that would indicate a short on the pin. The internal ASIC ground is constantly monitored against the remote sense negative pin. If the chip ground goes positive with respect to this pin, it indicates that the chip ground is open-circuit either inside the ASIC or the external wiring. The ASIC would be latched off, similar to an OV event.
AC Hysteresis
ACSENSE2
Soft-start VDD-OVP VDD-UVL AutoRestart Mode VREF-MON
GND-MON
Rev. A | Page 18 of 64
ADM1041 THEORY OF OPERATION
POWER MANAGEMENT
This block contains VDD undervoltage lockout circuitry and a power-on/reset function. It also provides precision references for internal use and a buffered reference voltage, VREF. If VREF is configured to an output pin, overloading, shorting to ground, or shorting to VDD do not effect the internal references. See Figure 8. During power-on, VREF does not come up until VDD exceeds the upper UVL threshold. Housekeeping functions in this block include reference voltage monitors, VDD overvoltage, and a ground fault detector. The ground fault detector monitors ADM1041 ground with respect to the remote sense pin VS-. If GND becomes positive with respect to VS- an on-chip signal, VDDOK, goes false. VDDOK is true only when all the following conditions are met: ground is negative with respect to VS-, INTREF and EXTREF are operating normally, VDD > UVLHI, and VDD < VDD OVP threshold.
GAIN TRIMMING AND CONFIGURATION
The various gain settings and configurations throughout the ADM1041 are digitally set up via the SMBus after it has been loaded onto its printed circuit board. There is no need for external trim potentiometers. An initial adjustment process should be carried out in a test system. Other adjustments such as current sense and voltage calibration should be carried out in the completed power supply.
VREF 18
VDD 1 MAIN BAND GAP
INTERNAL REFERENCE
2.5V
1.25V EXTREFOK
REFERENCE MONITOR
AUXILIARY REFERENCE 2.0V POR
INTREFOK
RESET
4.0V
UVLLO S VDDOK R Q
4.4V
UVLHI
6.0V-6.5V
OVP S 10s-20s 0.2V GROUND MONITOR GNDOK R Q Q
VDDOV
VS- 20 GND 7
gndok_dis
Figure 8. Block Diagram of Power Management Section
Rev. A | Page 19 of 64
04521-0-006
ADM1041
DIFFERENTIAL REMOTE SENSE AMPLIFIER
This amplifier senses the load voltage and is the main voltage feedback input. A differential input is used to compensate for the voltage drop on the negative output cable of the power supply. An external voltage divider should be designed to set the VS+ pin to approximately 2.0 V with respect to VS-. The amplifier gain is 1.0. See Figure 9.
LOCAL OVERVOLTAGE PROTECTION (OVP)
This is the main overvoltage detection for the power supply. It is detected locally so that only the faulty power supply shuts down in the event of an OVP condition in an N+1 redundant power system. This occurs only after a load OV event. The local OVP threshold may be trimmed via the SMBus. See Figure 9.
LOCAL UNDERVOLTAGE PROTECTION (UVP)
This is the main undervoltage detection for the power supply. It is also detected locally so that a faulty power supply can be detected in an N+1 redundant power system. The local UVP threshold may be trimmed via the SMBus. See Figure 9.
SET LOAD VOLTAGE
The load voltage may be trimmed via the SMBus by a trim stage at the output of the differential remote sense amplifier. The voltage at the output of the trimmer is 1.50 V when the voltage loop is closed. See Figure 9.
FALSE UV CLAMP
If a faulty power supply causes an OVP condition on the system bus, the control loops in the good power supplies is driven to zero output. Therefore, a means is required to prevent the good power supplies from indicating an undervoltage, and they must recover quickly after the faulty power supply has shut down. The false UV clamp achieves this by clamping the output voltage just above the local UVP threshold. It may be trimmed via the SMBus. The OCPF signal disables the clamp during overcurrent faults. See Figure 9.
LOAD OVERVOLTAGE (OV)
A comparator at the output of the load voltage trim stage detects load overvoltage. The load OV threshold can be trimmed via the SMBus. The main purpose is to turn off the OrFET when the load voltage rises to an intermediate overvoltage level that is below the local OVP level. This circuit is not latching. See Figure 9.
LOCAL VOLTAGE SENSE
This amplifier senses the output voltage of the power supply just before the OrFET. Its input is derived from one of the pins used for current sensing and is set to 2.0 V by an external voltage divider. The amplifier gain is 1.3. See Figure 9.
VS- REMOTE SENSE FROM LOAD
20 21
35k
35k 70A
VS+
35k
35k SET LOAD VOLTAGE 25k
CURRENT LIMIT DIFF. VOLTAGE SENSE CURRENT SHARE SET LOAD OVERVOLTAGE LOADVOK VREF 1.5V OCPF FALSE UV CLAMP SOFTSTART RAMP UP 1V 3V VOLTAGE ERROR AMP VCMP
5
CAPTURE
VLS 2
x1.3
1.25V
SET UV CLAMP THRESHOLD
SET OVP THRESHOLD
OVP 1.5V UVP
TO GENERAL LOGIC TO GENERAL LOGIC
04521-0-032
SET UVP THRESHOLD
NOTE: ALL POTENTIOMETERS (
) ARE DIGITALLY PROGRAMMABLE THROUGH REGISTERS.
Figure 9. Block Diagram of Voltage Sense Amplifier
Rev. A | Page 20 of 64
ADM1041
70
VOLTAGE ERROR AMPLIFIER
This is a high gain transconductance amplifier that takes its input from the load voltage trim stage described previously. The amplifier requires only the output pin for loop compensation, which typically consists of a series RC network-to-common. A parallel resistor may be added to common to reduce the openloop gain and thereby provide some output voltage droop as output current increases. The output of the amplifier is typically connected to an emitter follower that drives an optocoupler, which in turn controls the duty of the primary side PWM. The emitter follower should have a high gain to minimize loading effects on the amplifier. Alternatively, an op amp voltage follower may be used. See Figure 9, Figure 10, and Figure 11.
60 50
CURRENT (A)
40
30 20 10 0
0
1
2 VOLTAGE (V)
3
4
Figure 10. Current Limit
2.75 2.50 2.25 2.00 1.75
04521-0-039
MAIN VOLTAGE REFERENCE
A 1.5 V reference is connected to the inverting input of the voltage error amplifier. This 1.5 V reference is the output voltage of the soft-start circuit. Under closed-loop conditions, the voltage at the noninverting input is also controlled to 1.5 V. During start-up, the output voltage should be ramped up in a linear fashion at a rate that is independent of the load current. This is achieved by digitally ramping up the reference voltage by using a counter and a DAC. The ramp rate is configurable via the SMBus. See Figure 14.
04521-0-040
GM (mA/V)
1.50 1.25 1.00 0.75 0.50 0.25 0 1 10 100 1k 10k 100k BANDWIDTH 1M 10M
CURRENT SENSE AMPLIFIER
This is a two-stage differential amplifier that achieves low offset and accuracy. The amplifier has the option to be chopped to reduce offset or left as a linear amplifier without chopping. Refer to the Register Listing for more details. Its gain may be selected from three ranges. It is followed by a trim stage and then by a low gain buffer stage that can be configured with a gain of 1.0 or 2.1. The result is a total of six overlapping gain ranges (65 to 230), one of which must be selected via the SMBus. This gives ample adjustment to compensate for the poor initial tolerance of the resistance wires typically used for current sensing. It also allows selecting a higher sensitivity for better efficiency or a lower sensitivity for better accuracy (lower offset). The amplifier offset voltage is trimmed to zero in a once-off operation via the SMBus and uses a voltage controlled current source at the output of the first gain stage. A second controlled current source is used to trim out the additional offset due to the mismatch of the external divider resistors. This offset trim is dynamically adjusted according to the common-mode voltage present at the top of the voltage dividers. Six ranges are selectable according to the magnitude and polarity of this offset component. Because the offset compensation circuit itself has some inaccuracies, the best overall current sense accuracy is obtained by using more closely matched external dividers and then selecting a low compensation range. See Figure 14.
100M
Figure 11. VCMP Transconductance
220 200 180 160 140
GM (A/V)
120 100 80 60 40 20 0 1 10 100 1k 10k 100k BANDWIDTH 1M 10M
04521-0-041
100M
Figure 12. CCMP and SCMP Transconductance
Rev. A | Page 21 of 64
ADM1041
CURRENT SENSING
Current is typically sensed by a low value resistor in series with the positive output of the power supply, just before the OrFET or diode. For high voltages (12 V and higher), this resistor is usually placed in the negative load. A pair of closely matched voltage dividers connected to Pins 2 and 3 divide the commonmode voltage down to approximately 2.0 V. The divider ratio must be the same as used in the local and remote voltage sense circuits. Alternatively, current may be sensed by a current transformer (CT) connected to Pin 8. The ADM1041 must be configured via the SMBus to select one or the other. See Figure 13.
CURRENT SENSE CALIBRATION
Regardless of which means is used to sense the current, the end result of the calibration process should produce the standard current share signal between Pins 20 and 23, that is, 2.0 V at 100% load, excluding any additional share signal offset that might be configured.
CURRENT LIMIT ERROR AMPLIFIER
This is a low gain transconductance amplifier that takes its input from one of the calibrated current stages described previously. The amplifier requires only the output pin for loop compensation, which typically consists of a series RC network to common. A trimmable reference provides a wide range of adjustment for the current limit. When the current signal reaches the reference voltage, the output of the error amplifier comes out of saturation and begins to drive a controlled current source. The control threshold is nominally 1.0 V. This current flows through a resistor in series with the trimmed voltage loop signal and thereby attempts to increase the voltage signal above the 1.5 V reference for that loop. The closed voltage loop reacts by reducing the power supply's output voltage and this results in constant current operation. See Figure 13.
CURRENT TRANSFORMER INPUT
The ADM1041 can also be configured to sense current by using a current transformer (CT) connected to Pin 8. In this case, the resistive current sense is disabled. A separate single-ended amplifier has two possible sensitivities that are selected via the SMBus. If the CT option is selected, the gain of the 1.0, 2.1 buffer that follows the gain trim stage is no longer configurable and is fixed at 1.0. The share driver amplifier has a total of 100 mV positive offset built into it. In order to use the ADM1041 in CT mode, it is necessary to compensate for this additional 100 mV offset. This is achieved by adding in a positive offset on the CT input. This also allows any negative amplifier offsets in the CT chain to be nulled out. This offset cancellation is achieved by sourcing a current through a resistance on the ICT pin. The resistor value is 40 k and so for 100 mV of offset cancellation a current of 2.5 A is required. It is possible to fine trim this current via Register 15h, Bits 4-0, step size 170 nA. For example, 2.5 A 15 x 170 nA; so the code for Register 15h is decimal 15 or 0Fh. Refer to the Current Transformer parameter in the Specifications table for more details. See Figure 13.
OVERCURRENT PROTECTION
When the current limit threshold is reached, the OCP comparator detects when the current error amplifier comes out of saturation. Its threshold is nominally 0.5 V. This starts a timer that, when it times out, causes an OCP condition to occur and the power supply to shut down. If the current limit disappears before the time has expired, the timer is reset. The time period is configurable via the SMBus. Undervoltage blanking is applied during the timer operation. See Figure 14.
Rev. A | Page 22 of 64
OrFET GATE CURRENT OrFET SOURCE
REG 17h b7 GAIN = 10 CS+
3 2
VREF CURRENT SHARE OFFSET (VSHARE, IOUT = 0)
VDD
TO CURRENT SHARE DRIVE AMPLIFIER 9R
CS-/FS IRS/ICT SET CURRENT SHARE ICT
8
R
CURRENT LIMIT TO VOLTAGE ERROR AMP
Figure 13. Current Sense
40k
Rev. A | Page 23 of 64
TRANSFORMER CURRENT SENSE CONFIGURATION CURRENT TRANSFORMER CCMP
4
VREF SET CURRENT LIMIT LEVEL SET GAIN
CURRENT ERROR AMP
1.25V OCP 0.5V OCP COMPARATOR
04521-0-033
ADM1041
ADM1041 CURRENT SHARE
The current share method is the master-slave type, which means that the power supply with the highest output current automatically becomes the master and controls the share bus signal. All other power supplies become slaves, and the share bus signal causes them to increase their output voltages slightly until their output currents are almost equal to that of the master. This scheme has two major advantages. A failed master power supply simply allows one of the slaves to become the new master. A short circuited share signal disables current sharing, but all power supplies default to their normal voltage setting, allowing a certain degree of passive sharing. Because this chip uses a low voltage process, an external bidirectional amplifier is needed for most existing share bus signal levels. The voltage between Pins 20 and 23 is always controlled to 2.0 V full scale, ignoring any offset. By connecting Pins 20 and 23 together, the chip can produce a 2.0 V share signal directly without any external circuits. To improve accuracy, the share signal is referenced to remote voltage sense negative.
ISHARE ERROR AMPLIFIER
This is a low gain transconductance amplifier that measures the difference between the internal current share voltage and the signal voltage on the external share bus. If two power supplies have almost identical current share signals, a 50 mV voltage source on the inverting input helps arbitrate which power supply becomes the master and prevents "hunting" between master and slave roles. The amplifier requires only the output pin for loop compensation, which typically consists of a series RC network to common. When the power supply is a slave, the output of the error amplifier comes out of saturation and begins to drive a controlled current sink. The control threshold is nominally 1.0 V. This current flows from a resistor in series with the trimmed voltage loop signal and thereby attempts to decrease the voltage signal below the 1.5 V reference for that loop. The closed voltage loop reacts by increasing the power supply's output voltage until current share is achieved. The maximum current sink is limited so that the power supply voltage can be increased only a small amount, which is usually limited to be within the customer's specified voltage regulation limit. This small voltage increase also limits the control range of the current share circuit and is called the capture range. The capture range may be set via the SMBus to one of four values, from 1% to 4% nominal. See Figure 14.
CURRENT SHARE OFFSET
To satisfy some customer specifications, the current share signal can be offset by a fixed amount by using a trimmable current generator and a series resistor. The offset is added on top of the 2.0 V full-scale current share output signal. See Figure 14.
ISHARE DRIVE AMPLIFIER
This amplifier is a buffer with enough current source capability to drive the current share circuits of several slave power supplies. It has negligible current sink capability. Refer to the Differential Sense Amplifier section that follows.
ISHARE CLAMP
This clamp keeps the current share-loop compensation capacitor discharged when the current share is not required to operate. The clamp is released during power-up when the voltage reference and therefore the output voltage of the power supply has risen to either 75% or 88% of its final value. This is configurable via the SMBus. When the clamp is released, the current share loop slowly "walks in" the current share and helps to avoid output voltage spikes during hot swapping. See Figure 14.
DIFFERENTIAL SENSE AMPLIFIER
This amplifier has unity gain and senses the difference between the share bus voltage and the remote voltage sense negative pin. When the power supply is the master, it forms a closed loop with the ISHARE drive amplifier described above, and therefore it causes the share bus voltage between Pins 20 and 23 to equal the current share signal at the noninverting input of the ISHARE drive amplifier. When the power supply is a slave, the output of the differential sense amplifier exceeds the internal current share signal, which causes the ISHARE drive amplifier to be driven into cutoff. Because it is not possible to trim out negative offsets in the op amps in the current share chain, a 50 mV voltage source is used to provide a known fixed positive offset. The share bus offset controlled current source must be trimmed via the SMBus to take out the resulting overall offset. See Figure 14.
Share_OK DETECTOR
Incorrect current sharing is a useful early indicator that there is some sort of non-catastrophic problem with one of the power supplies in a parallel system. Two comparators are used to detect an excessive positive or negative error voltage at the input of the ISHARE error amplifier, which indicates that the current share loop has lost control. One of four possible error levels must be configured via the SMBus. See Figure 14.
Rev. A | Page 24 of 64
TO VOLTAGE ERROR AMP ISHARE ERROR AMPLIFIER SCMP
22
VREF CURRENT SHARE OFFSET (VSHARE, IOUT = 0) ISHARE CLAMP ISHARE DRIVE AMPLIFIER SHRO 9R
24
VDD
+12V GAIN = (R1 + R2)/R2 SHARE BUS 1N4148
FROM CURRENT SENSE
R SHAREOK CURRENT ERROR AMP
R1 60A
23
DIFFERENTIAL SENSE
SHRS+ VREF SET CURRENT LIMIT LEVEL 50mV R2
20
VS-/SHRS- 50mV GAIN = (R1+R2)/R2 REMOTE -VE SENSE
Figure 14. Current Share Circuit and Soft-start
Rev. A | Page 25 of 64
70A CURRENT LIMIT DIFF. VOLTAGE SENSE CURRENT SHARE 1V 3V CAPTURE VREF
VCMP
5
VOLTAGE ERROR AMP
04521-0-034
SOFT START RAMP UP
ADM1041
ADM1041
3V
2V VSHARE 1V OFFSET 0 0 20 40 60 IOUT 80 100%
04521-0-010
Figure 15. Load Share Characteristic
Rev. A | Page 26 of 64
ADM1041 PULSE/ACSENSE2
When configured, PULSE and ACSENSE monitor the output of the power main transformer. See Figure 16. The ac sense function monitors the amplitude of the incoming pulse and, if sufficiently high, generates a flag to indicate ac, or strictly speaking, the voltage on the bulk capacitor, is okay. Since the envelope of the pulse has a considerable amount of 100 Hz ripple, hysteresis is available on this input pin. Internally there is a 20 A to 80 A current sink. With a 909R external thevenin resistance, this current range translates to a voltage hysteresis of 200 mV to 500 mV. The internal hysteresis current is turned off when the voltage exceeds the reference on the comparator. This form of hysteresis allows simple scaling to be implemented by changing the source impedance of the pulse conditioning circuit. Some trimming of hysteresis and threshold voltage is provided. The ac sense function can be configured to be derived from ACSENSE2 rather than ACSENSE1. This allows a separate dc input from various locations to be used to generate AC_OK for better flexibility or accuracy.
PULSE
Providing the output of the pulse function (PULSE_OK) is high, the FET in the ORing circuit can be turned on. If the pulses stop for any reason, about 1 second later the PULSE_OK goes low and the OrFET drive is disabled. This delay allows passage of all expected pulse skipping modes that might occur in no load or very light load situations. See Figure 16.
ACSENSE
This is rarely used to measure directly the ac input to the supply. ACSENSE1 or ACSENSE2 are usually used to indirectly measure the voltage across the bulk capacitor so that the system can be signaled that power is normal. Also if power is actually lost, ACSENSE represents when just enough energy is left for an orderly shutdown of the power supply. See Figure 16.
TO OrFET SOURCE
TO CURRENT SENSE RESISTOR AND OrFET GATE
0.525V PULSEOK
S
9
Q
PULSE ACSENSE1
5.3k SELECT ACSENSE
R
CLK Q 1 SEC
R
ACSENSE2 10
1.5V 5.3k
AC_OK
S CLK Q 1 mS R
Q
R
Figure 16. Pulse In and AC Sense Circuit
Rev. A | Page 27 of 64
04521-0-035
TRIM HYSTERESIS
ADM1041
OrFET GATE DRIVE
When configured, this block provides a signal to turn on/off an OrFET used in the output of paralleled power supplies. The gate drive voltage of one of these FETs is typically 6 V to 10 V above the output voltage. Since the output voltage of the ADM1041 is limited, an external transistor needs to be used. The block diagram shows an example of this approach. See Figure 21. The FG output is an open-drain, N-channel MOSFET and is normally high, which holds the OrFET off. When all the startup conditions are correct, Pin 19 is pulled low, which allows the OrFET to turn on. The logic can also be configured as inverted if a noninverting drive circuit is used. A differential amplifier monitors the voltage across the OrFET and has two major functions. First, during start-up, it allows the OrFET to turn on with almost 0 V across it to avoid voltage glitches on the bus. This applies to a hot bus or a cold bus. The internal threshold can be configured from 20 mV to 50 mV (negative), which is scaled up by the external voltage dividers. Second, if a rectifier or filter capacitor fails during steady state operation, it detects the resulting reverse voltage across the OrFET's on-resistance and turns off the OrFET before a voltage dip appears on the bus. The internal threshold can be configured from 100 mV to 250 mV (negative), which is also scaled up by the external voltage dividers. A slightly larger filter capacitor may be used on the voltage divider at Pin 6 to speed up this function. Figure 17 shows the typical response time of the ADM1041 to such an event. In the plot, VFD is ramped down and the response time of the FG pin to a reverse voltage event on the FD pin is seen. This simulates the rectifier or filter capacitor failure during steady state operation. When the FD voltage is below 1.9 V (2 V minus 100 mV threshold), the FG pin reacts. As can be seen, the response time is approx 330 nsecs. This extremely fast turn-off is vital in an n+1 power supply system configuration. It ensures that the damaged power supply removes itself from the system quickly. Figure 18 is the equivalent response time to turn on the OrFET. As can be seen, there is a delay of approximately 500 ns before the FG pin ramps down to turn on the OrFET, and therefore allow the power supply to contribute to the system. This propagation delay is due mainly to internal amplifier response limitations. The circuit in Figure 21 is used to generate these plots. In this case, the resistor to VDD from the FG pin is 2 k. Figure 19 and Figure 20 show the OrFET turn-off time and turn-on time when the FG pin polarity is inverted. As can be seen, to turn off the OrFET, the VFG pin now transitions from high to low. Also, its corresponding turn-on event occurs from a low-to-high transition. The circuit in Figure 21 is used to generate these plots.
TTOTAL = 506ns
04521-0-013
TTOTAL = 330ns
64%
04521-0-042
TDELAY = 218ns T = 112ns
Figure 17. OrFET Turn-Off Time (Default Polarity)
Figure 18. OrFET Turn-On Time (Default Polarity)
Rev. A | Page 28 of 64
ADM1041
TTOTAL = 618ns
64%
04521-0-043 04521-0-044
TTOTAL = 222ns
TDELAY = 506ns
T = 112ns
Figure 19. OrFET Turn- Off Time (Inverse Polarity)
Figure 20. OrFET Turn-On Time (Inverse Polarity)
CURRENT VOUT SOURCE V = VOUT +10V GATE DRAIN
2
6
FS
FD FG
VDD
PULSEOK LOADOK PENOK REVERSEOK OrFET OK RESET VOLTAGE DETECTOR
19
POLARITY
VREF
Figure 21. OrFET Gate Drive Circuit
Rev. A | Page 29 of 64
04521-0-036
ADM1041 OSCILLATOR AND TIMING GENERATORS
An on-board oscillator is used to generate timing signals. Some trimming of the oscillator is provided to adjust for variations in processing. All timing generated from the oscillator is expected to meet the same tolerances as the oscillator. Since individual delay counters are generally two to three bits, the worst error is one clock period into these counters, which is 25% of the nominal delay period. None of these tolerances are extremely critical.
MON1
This is the alternative analog comparator function for the Pulse/ACSENSE1 pin (Pin 9). The threshold is 1.25 V. When MON1 is selected, ACSENSE1 defaults to true.
MON2
This is the alternative analog comparator function for the ACSENSE2 pin (Pin 10). The threshold is 1.25 V. When MON2 is selected, ACSENSE2 defaults to true.
LOGIC I/O AND MONITOR PINS
Apart from pins required for the various key analog functions, a number of pins are used for logic level I/O signals. If the logic I/O function is not required, the pins may be reconfigured as general-purpose comparators for analog level monitoring (MON) and may be additionally configured to have typical OVP and UVP properties, either positive-going or negative-going, depending on whether a positive supply output or a negative supply output is being monitored. When monitoring negative outputs, a positive bias must be applied via a resistor to VREF. The status of all protection and monitoring comparators are held in registers that can be read by a microprocessor via the SMBus. Certain control bits may be written to via the SMBus.
PEN
This is the power enable pin that turns the PWM converter on and can be configured as active high or low. This might drive an opto-isolator back to the primary side or connect to the enable pin of a secondary-side post regulator.
PSON
This pin is usually connected to the customer's PSON signal and, when asserted, causes the ADM1041 to turn on the power output. It can be configured as active high or low. Alternatively, a microprocessor can communicate the PSON function to the ADM1041 using the SMBus. Or the PSONLINK signal may be used. When the PSON pin is not used as such it can be configured as an analog input, MON3.
CBD/ALERT
This pin can be used either as a crowbar driver or as an SMBus alert signal to indicate that a fault has occurred. It is typically configured to respond to a variety of status flags, as detailed in Registers 1Ah and 1Bh. The primary function of this pin is as a crowbar driver, and as such it should be configured to respond to the OV fault status flag. It can be configured to respond to any or all of a variety of fault status flags, including a microprocessor writable flag, and can be configured as latching or nonlatching. It may also be configured as an open-drain N-channel or P-channel MOSFET and as positive or negative (inverted) logic. A pull-up or pull-down resistor is required. This pin may be wire-ORed with the same pin on other ADM1041 ASICs in the power supply. The alternative function is an SMBus alert output that can be used as an interrupt to a microprocessor. If a fault occurs, the microprocessor can then query the ADM1041(s) about the fault status. This is intended to avoid continuously polling the ADM1041(s). Generally, the microprocessor needs to routinely gather other data from the ADM1041(s), which can include the fault status, so the ALERT function may not be used. Also, the simplest microprocessors may not have an interrupt function. This allows the CBD/ALERT pin to be used for other functions.
MON3
This is the alternative analog comparator function for the PSON pin (Pin 16). The threshold is 1.25 V. When MON3 is selected, PS ON defaults to off.
DC_OK (PW-OK, PWR Good, Etc.)
This output is true when all dc output voltages are within tolerance and goes false to signify an imminent loss of power. Timing is discussed later. It can be configured as an open-drain Nchannel or P-channel MOSFET and as positive or negative (inverted) logic. A pull-up or pull-down resistor is required. This pin may be wire-ORed with the same pin on other ADM1041 ASICs in the power supply. When the DC_OK pin is not used as such, it can be configured as an analog input, MON4.
MON4
This is the alternative analog comparator function for the DC_OK pin (Pin 17). The threshold is 1.25 V.
VREF
This pin normally provides a precision 2.5 V voltage reference. Alternatively, it can be configured as the AC_OK output or as an analog input, MON5. A load capacitance of 1 nF (typ) is recommended on VREF.
Rev. A | Page 30 of 64
ADM1041
AC_OK
This output is true when either ACSENSE1 or ACSENSE2 is true (configurable). It can be configured as an open-drain N-channel or P-channel MOSFET and as positive or negative (inverted) logic. A pull-up or pull-down resistor is required. This pin can be wire-ORed with the same pin on other ADM1041 ASICs in the power supply. When the AC_OK pin is not used as such, it can be configured as an analog input, MON5, or as a voltage reference.
+5V
1
VCC
MON2 10
MON3 16
MON5 18
7
-12V THERMISTOR
04521-0-016
MON5
This is the alternative analog comparator function for the AC_OK/VREF pin (Pin 18). The threshold is 2.5 V, and it has a 100 A current source that allows hysteresis to be controlled by adjusting the external source resistance. It is ideal for an OTP sensing circuit using a thermistor as part of a voltage divider. The OTP condition can be configured to latch off the power supply (similar to OVP) or to allow an auto-restart (soft OTP). See Figure 22.
OCP 2.5V 2.5V
Figure 22. Example of MON Pin Configuration
In the preceding example, MON2 and MON3 are configured to monitor a negative 12 V rail. MON2 is configured as negative going OVP, and MON3 is configured as positive going UVP. The 5 V power rail is used for bias voltage.
18
OTP/ MON5
OCP
MON5
1.25V 1.5V OVP OVP
10 MON2 9
MON1
MON1
MON2 UVP UVP GENERAL LOGIC ACOK ORFETOK SHAREOK RESET VDDOK VDDOV PENOK ACOK ORFETOK SHAREOK RESET VDDOK VDDOV PENOK DC_OK CBD CONTROL REGISTERS PWRON MON4
16 PSON 16 MON3
MON3
17 MON4
PSON CLOCK VREF AC_OK
18 VREF
18 AC_OK
17 DC_OK
11 CBD/ALERT
PEN
12 PEN
CONFIGURE I/Os CONFIGURE STATUS (WRITE (READ REGISTERS) REGISTERS) SDA/ SCL CS
04521-0-014
CONTROL SERIAL LINES INTERFACE
PEN
14 PS LINK ON 13 SCL/
AC_OKLink
15 ADD0
Figure 23. Block Diagram of Protection and General Logic
Rev. A | Page 31 of 64
mn1s i2cmb ACSENSE acsns acsok uvbm DEBOUNCE 1ms scl_in set_cshare_clamp ssr1s1, ssrs0 VREF 1.5V error_amp inv input psonlink SCL/ AC_OKLink (13) GM psonts1.psonts0 VCMP (5) VOLTAGE ERROR AMP m_acsns_w
acss
ADM1041
ACSENSE1/ MON1 (9)
CONFIG
mn2s
ACSENSE2/ MON2 (10)
CONFIG
acsns_hyst acsns_thresh
mn3s 0, 40, 80, 160ms up_pson_m sda_in SDA/ PSONLINK (14) m_shr_clmp 300s, 10ms, 20ms, 40ms 75%/88%
m_pson_w
m_pson_r SOFT START RAMP
PSON3/ MON3 (12)
CONFIG
SOFT START VOUT DAC scmp_in
SCMP (22)
mov5
softotp sda_out
clamp
rsm restartb SQ m_psonok_r R dcokoff_delay gatepen penon vddok DC_OK OFF DELAY 0, 1, 2, 4ms QS R muv1 muv2 muv3 uvok 450s 200, 400, 800, 1600ms muv4 muv5 localuv UV BLANK uvfault RQ 80ms ocfault ocpts2, ocpts1, ocpts0 shareok selcbd1<0> orfetok selcbd1<1> opt(mov5) selcbd1<2> ovfault softotp mov5 mov1 mov2 mov3 mov4 vddov local ov ocpf selcbd1<3> acsns selcbd1<4> ocpto selcbd1<5> uvfault selcbd1<6> ovfault selcbd1<7> NOT USED selcbd2<0> mfg5 selcbd2<1> m_cbd_w selcbd2<2> mfg4 selcbd2<3> mfg3 selcbd2<4> mfg2 selcbd2<5> mfg1 selcbd2<6> vddok selcbd2<7> FAULT FAULTB SQ UV DEBOUNCE POKTS1, POKTS0 DC_OK ON DELAY
gateramp
1 SECOND
polpen m_penok_r DRIVER PEN (12)
poldcok, mn4s0 m_dcok_r
Figure 24. General Logic
Rev. A | Page 32 of 64
OCP DISABLE OCP RIDETHROUGH 128, 256, 384, 512s, OR 1, 2, 3, 4SEC
DRIVER
DC_OK/ MON4 (17)
FROM OUTPUT OF CURRENT ERROR AMP
OCP
COMP (4)
OCPF
0.5V
curr_lim_dis
polcbd cbdlm DRIVER CBD/ ALERT (11)
S D Q
m_cbd_cir por
R
04521-0-015
ADM1041
SMBus SERIAL PORT
The programming and microprocessor interface for the ADM1041 is a standard SMBus serial port, which consists of a clock line and a data line. The more rigorous requirements of the SMBus standard are specified in order to give the greatest noise immunity. The ADM1041 operates in slave mode only. If a microprocessor is not used, these pins can be configured to perform the PSONLINK and AC_OKLink functions. Note that this port is not intended to be connected to the customer's SMBus (or I2C bus). Continuous SMBus activity or an external bus fault interferes with the inter-ASIC communication, possibly preventing proper operation and proper fault reporting. If the customer needs status and control functions via the SMBus, it is recommended that a microprocessor with a hardware SMBus (I2C) port be used for this interface. The microprocessor should access the ASICs via a second SMBus port, which may be emulated in software (subset of the full protocol).
MICROPROCESSOR SUPPORT
The ADM1041 has many features that allow it to operate with the aid of a microprocessor. There are several reasons why a microprocessor might be used: * * * To provide unusual logic and/or timing requirements, particularly for fault conditions. To drive one or more LEDs, including flashing, according to the status of the power supply. To replace other discrete circuits such as multiple OTP, extra output monitoring, fan speed control, and failure detection, and combine the status of these circuits with the status of the ADM1041s. To free up some pins on the ADM1041s. This could reduce the number of ASICs and therefore the cost. To interface to an external SMBus (or I2C) for more detailed status reporting. The SMBus port in the ADM1041 is not intended for this purpose. To allow EEPROM space in ADM1041(s) or in the microprocessor to be used for FRU (VPD) data. A simple or complex microprocessor can be used according to the amount of additional functionality required. Note that the microprocessor is not intended to access or modify the EEPROM address space that is used for the configuration of the ADM1041(s).
* *
SDA/PSONLINK
The SDA pin normally carries data in and out of the ASIC during programming/configuration or while reading/writing by a microprocessor. If a microprocessor is not used, this pin can be configured as PSONLINK and can be connected to the same pin on other ADM1041s in the power supply. If a fault is detected in any ADM1041, causing it to shut down, it uses this pin to signal the other ADM1041s to also shut down. If an autorestart has been configured, it also causes all ADM1041s to turn on together. *
SCL/AC_OKLink
The SCL pin normally provides a clock signal into the ASIC during programming/configuration or while reading/writing by a microprocessor. If a microprocessor is not used, this pin can be configured as AC_OKLink, and can be connected to the same pin on other ADM1041s in the power supply. This allows a single ADM1041 to be used for ac sensing and helps to synchronize the start-up of multiple ADM1041s.
Interfacing
The microprocessor must access the ADM1041(s) via their on-board SMBus (I2C) port. Since this port is also used for configuration of the ADM1041(s), the software must include a routine that avoids SMBus activity during the configuration process. The simplest interface is for the microprocessor to have an SMBus (I2C) port implemented in hardware, but this may be more expensive. An alternative is to emulate the bus in software and to use two general-purpose logic I/O pins. Only a simple subset of the SMBus protocol need be emulated because the ADM1041 always operates as a slave device.
ADD0
This pin configures two bits of the chip address for the SMBus. It is three-level and can be pulled high to VDD, pulled low to ground, or left floating (internally biased to 2.5 V). An additional bit may be set during configuration, which allows up to six ADM1041s to be used in a single power supply. The state of ADD0 is continuously sampled after VDD power-up. After the first time the ADM1041 is successfully addressed, the internal bias is released and ADD0 becomes high impedance.
Configuring for a Microprocessor
Except during initial configuration, all ADM1041 registers that need to be accessed are high speed CMOS devices that do not involve EEPROM. The Microprocessor Support table (Table 43) details the various registers, bits, and flags that can be read and written to, including explanations. Note that for the microprocessor to gain control of the PSON and ACSENSE functions, the normal signal path in the ADM1041 must be configured to be broken. A separate configuration bit is allocated to each signal. The microprocessor can then write to the signal after the break as though the signal originated within the ADM1041 itself. The original signals can still be read prior to the break.
Rev. A | Page 33 of 64
ADM1041
BROADCASTING
In a power supply with multiple outputs, it is recommended that all outputs rise together. Because the SMBus is relatively slow, simply writing sequentially to the PSON signal in each ADM1041, for instance, causes a significant delay in the output rise of the last chip to be written. The ADM1041 avoids this problem by allocating a common broadcast address that all chips can respond to. To avoid data collisions, this feature should be used only for commands that do not initiate a reply. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, then the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data, followed by an Acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-tohigh transition when the clock is high may be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction such as telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. Because data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it might be necessary to first do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the tenth clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as No Acknowledge. The master then takes the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a stop condition.
SMBus SERIAL INTERFACE
Control of the ADM1041 is carried out via the SMBus. The ADM1041 is connected to this bus as a slave device under the control of a master device. The ADM1041 has a 7-bit serial bus slave address. When the device is powered up, it does so with a default serial bus address. The default power-on SMBus address for the device is 1010XXX binary, the three lowest address bits (A2 to A0) being defined by the state of the address pin, ADD0, and Bit 1 of Configuration Register 4 (ADD1). Because ADD0 has three possible states (tied to VDD, tied to GND, or floating) and Config4 < 1 > can be high or low, there are a total of six possible addresses, as shown in Table 6.
GENERAL SMBus TIMING
The SMBus specification defines specific conditions for different types of read and write operation. General SMBus read and write operations are shown in the timing diagrams of Figure 25, Figure 26, and Figure 27, and described in the following sections. The general SMBus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that a data stream will follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first), plus a R/W bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read).
Note: If it is required to perform several read or write operations in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation.
Rev. A | Page 34 of 64
ADM1041
19 SCLK 9 1 9
SDATA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADM1041
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADM1041
FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCLK (CONTINUED)
FRAME 2 ADDRESS POINTER REGISTER BYTE 9
SDATA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
04521-0-045
ACK. BY ADM1041 FRAME 3 DATA BYTE
STOP BY MASTER
Figure 25. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1 SCLK
9
1
9
SDATA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADM1041
D7
D6
D5
D4
D3
D2
D1
D0
04521-0-046
04521-0-047
ACK. BY ADM1041 FRAME 2 ADDRESS POINTER REGISTER BYTE
STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
Figure 26. Writing to the Address Pointer Register Only
1 SCLK
9
1
9
SDATA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADM1041
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADM1041 STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE FROM ADM1041
Figure 27. Reading Data from a Previously Selected Register
Table 6. Device SMBus Addresses
ADD1 0 0 0 1 1 1 ADD0 GND VDD NC GND VDD NC A2 0 0 1 0 0 1 A1 0 0 0 1 1 0 A0 0 1 0 0 1 1 Target Device 0 1 4 2 3 5
Note: ADD1 is low by default. To access the additional three addresses it is necessary to set Config 4 < 1 > high and then perform a power cycle to allow the new address to be latched after the EEPROM download. Refer to the section on Extended SMBUS Addressing for more details.
Rev. A | Page 35 of 64
ADM1041
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1041 contains volatile registers (RAM) and nonvolatile EEPROM. RAM occupies the address locations from 00h to 7Fh, while EEPROM occupies the address locations from 8000h to 813Fh. The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADM1041 are discussed in the next sections. The following abbreviations are used in the diagrams: S--START P--STOP R--READ W--WRITE A--ACKNOWLEDGE A--NO ACKNOWLEDGE The ADM1041 uses the following SMBus write protocols. The EEPROM page address consists of the EEPROM address high Byte 80h for FRU or 81h for register default and the three MSBs of the low byte. The lower five bits of the EEPROM address of the low byte are ignored during an erase operation.
1 2 3 4 5 6 7 8 9 10 11 12
04521-0-019
EEPROM EEPROM ADDRESS ADDRESS COMMAND A2h ARBITRARY SLAVE WA A A A AP S HIGH BYTE LOW BYTE (PAGE ERASE) DATA ADDRESS (80h OR 81h) (00h TO FFh)
Figure 28. EEPROM Page Erase Operation
Page erasure takes approximately 20 ms. If the EEPROM is accessed before erasure is complete, the SMBus responds with No Acknowledge. Figure 29 shows the peak IDD supply current during an EEPORM page erase operation. Decoupling capacitors of 10 F and 100 nF are recommended on VDD.
SMBus Erase EEPROM Page Operations
EEPROM memory can be written to only if it is effectively unprogrammed. Before writing to one or more locations that are already programmed, the page containing those locations must be erased. EEPROM ERASE is performed by sending a page erase command byte (A2h) followed by the page location of what you want to erase. (There is no need to set an erase bit in an EEPROM control/status register.) The EEPROM consists of 16 pages of 32 bytes each; the register default EEPROM consists of 1 page of 32 bytes starting at 8100h. Table 7. EEPROM Page Layout
Page No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EEPROM Location 8000h to 801Fh 8020h to 803Fh 8040h to 8050h 8060h to 8070h 8080h to 8090h 80A0h to 80BFh 80C0h to 80DFh 80E0h to 80FFh 8100h to 811Fh 8120h to 813Fh 8140h to 815Fh 8160h to 817Fh 8180h to 819Fh 81A0h to 81BFh 81C0h to 81DFh 81E0h to 81FFh Description Available FRU Available FRU Available FRU Available FRU Available FRU Available FRU Available FRU Available FRU Configuration Boot Registers ADI Registers Available FRU Available FRU Available FRU Available FRU Available FRU ADI Registers
Figure 29. EEPROM Page Erase Peak IDD Current
SMBus Write Operations
Send Byte In this operation, the master device sends a single command byte to a slave device, as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master asserts a stop condition on SDA and the transaction ends.
Rev. A | Page 36 of 64
04521-0-020
ADM1041
In the ADM1041, the send byte protocol is used to write a register address to RAM for a subsequent single-byte read from the same address or block read or write starting at that address. This is illustrated in Figure 30.
1 2 3 4 56 1
04521-0-021
*
Set up a 2-byte EEPROM address for a subsequent read or block read. In this case, the command byte is the high byte of the EEPROM address (80h). The (only) data byte is the low byte of the EEPROM address. This is illustrated in Figure 32.
2 3 4 5 6 78
04521-0-023
RAM SLAVE S W A ADDRESS A P ADDRESS (00h TO 7Fh)
EEPROM EEPROM ADDRESS ADDRESS SLAVE S WA A AP HIGH BYTE LOW BYTE ADDRESS (80h OR 81h) (00h TO FFh)
Figure 30. Setting a RAM Address for Subsequent Read Figure 32. Setting an EEPROM Address
If it is required to read data from the RAM immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single-byte read, block read, or block write operation without asserting an intermediate stop condition. Write Byte/Word In this operation, the master device sends a command byte and one or two data bytes to the slave device, as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low).
1
If it is required to read data from the EEPROM immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single-byte read or a block read without asserting an intermediate stop condition. * Write a single byte of data to EEPROM. In this case, the command byte is the high byte of the EEPROM address, 80h or 81h. The first data byte is the low byte of the EEPROM address and the second data byte is the actual data. Bit 1 of EEPROM Register 3 must be set. This is illustrated in Figure 33.
2 3 4 5 6 7 8 DATA 9 10 AP
04521-0-024
The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master sends a data byte. The slave asserts ACK on SDA. The master sends a data byte (or may assert stop at this point). The slave asserts ACK on SDA.
EEPROM EEPROM ADDRESS ADDRESS SLAVE S WA A A HIGH BYTE LOW BYTE ADDRESS (80h OR 81h) (00h TO FFh)
Figure 33. Single-Byte Write to EEPROM
If it is required to read data from the ASIC immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single-byte read, block read, or block write operation without asserting an intermediate stop condition.
Block Write
In this operation, the master device writes a block of data to a slave device. Programming an EEPROM byte takes approximately 300 s, which limits the SMBus clock for repeated or block write operations. The start address for a block write must have been set previously. In the case of the ADM1041, this is done by a send byte operation to set a RAM address or by a write byte/ word operation to set an EEPROM address. 1. 2. 3. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code that tells the slave device to expect a block write. The ADM1041 command code for a block read is A0h (10100000). The slave asserts ACK on SDA.
10. The master asserts a stop condition on SDA to end the transaction. In the ADM1041, the write byte/word protocol is used for the following three purposes. The ADM1041 knows how to respond by the value of the command byte. * Write a single byte of data to RAM. In this case, the command byte is the RAM address from 00h to 7Fh and the (only) data byte is the actual data. This is illustrated in Figure 31.
1 S 2 3 4 5 6 DATA 78 AP
04521-0-022
SLAVE WA ADDRESS
RAM ADDRESS A (00h TO 7Fh)
4.
Figure 31. Single-Byte Write to RAM
5.
Rev. A | Page 37 of 64
ADM1041
6. The master sends a data byte that tells the slave device how many data bytes will be sent. The SMBus specification allows a maximum of 32 data bytes to be sent in a block write. The slave asserts ACK on SDA. The master sends N data bytes. The slave asserts ACK on SDA after each data byte.
Block Read In this operation, the master device reads a block of data from a slave device. The start address for a block read must previously have been set. In the case of the ADM1041, this is done by a send byte operation to set a RAM address or by a write byte/word operation to set an EEPROM address. The block read operation itself consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeat start, and a read operation that reads out multiple data bytes, as follows: 1.
04521-0-025
7. 8. 9.
10. The master asserts a stop condition on SDA to end the transaction.
1 2 3 4 5 6
The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code that tells the slave device to expect a block read. The ADM1041 command code for a block read is A1h (10100001). The slave asserts ACK on SDA. The master asserts a repeat start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The slave asserts ACK on SDA. The master receives a byte count data byte that tells it how many data bytes will be received. The SMBus specification allows a maximum of 32 data bytes to be received in a block read.
7
8
9
10
2. 3. 4.
BYTE COMMAND A0h SLAVE S WA A A DATA 1 A DATA 2 A DATA N A P COUNT (BLOCK WRITE) ADDRESS
Figure 34. Block Write to EEPROM or RAM
When performing a block write to EEPROM, the page that contains the location to be written should not be writeprotected (Register 03h) prior to sending the above SMBus packet. Block writes are limited to within a 32-byte page boundary and cannot cross into the next page.
5. 6. 7. 8. 9.
SMBus READ OPERATIONS
The ADM1041 uses the following SMBus read protocols. Receive Byte In this operation, the master device receives a single byte from a slave device, as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts ACK on SDA. The master receives a data byte. The master asserts NO ACK on SDA. The master asserts a stop condition on SDA and the transaction ends.
10. The master asserts ACK on SDA. 11. The master receives N data bytes. 12. The master asserts ACK on SDA after each data byte. 13. The slave does not acknowledge after the Nth data byte. 14. The master asserts a stop condition on SDA to end the transaction.
In the ADM1041, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has been set previously by a send byte or write byte/ word operation. This is illustrated in Figure 35.
SLAVE RA S ADDRESS DATA AP
04521-0-026
1
2
3
4
56
Figure 35. Single-Byte Read from EEPROM or RAM
04521-0-027
1
S
2
3
4
56
7
8
9
10
11
12
13 14
COMMAND A1h BYTE SLAVE SLAVE RA A DATA 1 A DATA N A P AS WA (BLOCK READ) COUNT ADDRESS ADDRESS
Figure 36. Block Read from EEPROM or RAM
Rev. A | Page 38 of 64
ADM1041
Notes on SMBus Read Operations The SMBus interface of the ASIC cannot load the SMBUS if no power is applied to the ASIC. This requirement allows a power supply to be disconnected from the ac supply while still installed in a power subsystem. When using the SMBus interface, a write always consists of the ADM1041 SMBus interface address byte, followed by the internal address register byte, and then the data byte. There are two cases for a read: * If the internal address register is known to be at the desired address, simply read the ASIC with the SMBus interface address byte, followed by the data byte read from the ASIC. The internal address pointer increments if a block mode operation is in progress; data values of 0 are returned if the register address limit of 7Fh is exceeded, or if unused registers in the address range 00h to 7Fh are accessed. If the address register is pointing at EEPROM memory, that is 8000h, and the address reaches its limit of 80FFh, it does not roll over to Address 8100h on the next access. Additional accesses do not increment the address pointer, all reads return 00h, and all writes complete normally but do not change any internal register or EEPROM location. If the address register is pointing at EEPROM memory, that is 81xxh, and the address reaches its limit of 813Fh, it does not roll over to Address 8140h on the next access. Additional accesses do not increment the address pointer, all reads return 00h, and all writes complete normally but not change any internal register or EEPROM location. Note that for byte reads, the internal address does not auto increment. * If the internal address register value is unknown, write to the ADM1041 with the SMBus interface address byte, followed by the internal address register byte. Then restart the serial communication with a read consisting of the SMBus interface address byte, followed by the data byte read from the ADM1041. If more than one device is asserting an alert, all alerting devices try to respond with their slave addresses, but an arbitration process ensures that only the lowest slave address is received by the master. If the slave device has its alert configured as latching, it sends a command via the SMBus to clear the latch. The master should then check if the alert line is still asserted, and, if so, repeat the ARA call to service the next alert. Note that an alerting slave does not respond to an ARA call unless it is configured in SMBus mode (not AC_OKLink/PSONLINK) and up_pson_m is set. The ADM1041 supports the SMBus (ARA) function.
SUPPORT FOR SMBus 1.1
SMBus 1.1 optionally adds a CRC8 frame check sequence to check if transmissions are received correctly. This is particularly useful for long block read/write EEPROM operations, when the SMBus is heavily loaded or in a noisy environment. The CRC8 frame can be used to guarantee reliability of the EEPROM.
LAYOUT CONSIDERATIONS
Noise coupling into the digital lines (greater than 150 mV), overshoot greater than VCC and undershoot less than GND may prevent successful SMBus communication with the ADM1041. SMBus No Acknowledge is the most common symptom, causing unnecessary traffic on the bus. Although the SMBus maximum frequency of communication is rather low (400 kHz max), care still needs to be taken to ensure proper termination within a system with multiple parts on the bus and long printed circuit board traces. A 5.1 k resistor can be added in series with the SDA and SCL lines to help filter noise and ringing. Minimize noise coupling by keeping digital traces out of switching power supply areas and ensure that digital lines containing high speed data communications cross at right angles to the SDA and SCL lines.
POWER-UP AUTO-CONFIGURATION
After power-up or reset, the ADM1041 automatically reads the content of a 32-byte block of EEPROM memory that starts at 8100h and transfers the contents into the appropriate trim-level and control registers (00h to 1Bh). In this way, the ADM1041 can be preconfigured with the desired operating characteristics without the host system having to download the data over the SMBus. This does not preclude the possibility of modifying the configuration during normal operation. Figure 37 shows a block diagram of the EEPROM download at power-up or power-on reset.
EEPROM RAM CONFIGURATION REGISTERS DIGITAL TRIM POTS
SMBus ALERT RESPONSE ADDRESS (ARA)
The ADM1041's CBD/ALERT pin can be configured to respond to a variety of fault signals and can be used as an interrupt to a microprocessor. The pins from several ADM1041s may be wireORed. When the SMBus master (microprocessor) detects an alert request, it normally needs to read the alert status of each device to identify the source of the alert. The SMBus ARA provides an easier method to locate the source of a such an alert. When the master receives an alert, it can send a general call address (0001100) over the bus. The device asserting the alert responds by returning its own slave address to the master.
POWER UP
Figure 37. EEPROM Download
Rev. A | Page 39 of 64
04521-0-028
DIGITAL TIMING CONTROL
ADM1041
EXTENDED SMBus ADDRESSING
A potential problem exists when using more than three ADM1041s in a single power supply. The first time the device is powered up, Bit 1 of Configuration Register 1 (ADD1) is 0. This means that only three device addresses are initially available defined by ADD0; if there are more than three devices in a system, two or more of them will have duplicate addresses. See Figure 38. To overcome this problem, the ICT pin has additional functionality. Taking ICT below GND temporarily disables the SMBus function of the device. Thus, if the ICT pin of all devices in which ADD1 is to remain 0 are taken negative, the ADD1 bits of all other devices can be set to 1 via the SMBus. Each device then has a unique address. Internal diodes clamp the negative voltage to about 0.6 V, and care should be taken to limit the current to less than approximately 5 mA on each ICT input to prevent the possibility of damage or latch-up. The suggested current is 3 mA. One example of a suitable circuit is given in Figure 38. The ADM1041s can then be configured and trimmed. If required, AC_OKLink and PSONLINK must be configured last. If ICT is used for its intended purpose as a current transformer input, care must be taken with the circuit design to allow the extended SMBus addressing to work.
VDD
ICT 8 SCL 13 N/C 15 ADD0 SDA 14
AC_OKLink PSONLink
DEVICE 5
ICT 8 VDD
15 ADD0
ADD1 = 1
SCL 13 SDA 14
DEVICE 4
ICT 8 SCL 13
15 ADD0
SDA 14
DEVICE 3 4k ICT 8 SCL 13 N/C 15 ADD0 SDA 14 2.4mA DEVICE 2 EXTENDED SMBus ADDRESSING -12V VDD
15 ADD0
BACKDOOR ACCESS
After SCL and SDA have been configured as AC_OKLink and PSONLINK, it may be desired to recover the SMBus access to the ADM1041. Changes may be necessary to the internal configuration or trim bits. This is achieved by holding the SCL and SDA pins at 0 V (ground) while cycling VDD. SCL and SDA then revert to SMBus operation. See Figure 38.
4k ICT 8 ADD1 = 0 SCL 13 SDA 14
DEVICE 1 4k ICT 8 SCL 13
15 ADD0
SDA 14
DEVICE 0
04521-0-029
BACKDOOR
Figure 38. Extended SMBus Addressing and Backdoor Access
Rev. A | Page 40 of 64
ADM1041 REGISTER LISTING
Table 8.
Register Address 00h/2Ah 01h/2Bh 02h/2Ch 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 20h-29h 2Ah 2Bh 2Ch 2Dh-2Eh 8000h-81FFh Name Status1/Status1 Mirror Latched Status2/Status2 Mirror Latched Status3/Status3 Mirror Latched Calibration Bits Current Sense CC Current Share Offset Current Share Slope EEPROM_lock Load OV Fine Local UVP Trim Local OVP Trim OTP Trim ACSNS Trim Config1 Config2 Config3 Config4 Config5 Config6 Config7 Current Sense Divider Error Trim Current Sense Amplifer Offset Trim Current Sense Config 1 Current Sense Config 2 UV Clamp Trim Diff Sense Trim Sel CBD/SMBAlert1 Sel CBD/SMBAlert2 Manufacturer's ID Revision Register Reserved for Manufacturer Status1 Mirror Latched Status2 Mirror Latched Status3 Mirror Latched Reserved for Manufacturer EEPROM Power-On Value XXh--Depends on status of ADM1041 at power-up. XXh--Depends on status of ADM1041 at power-up. XXh--Depends on status of ADM1041 at power-up. From EEPROM Register 8103h From EEPROM Register 8104h From EEPROM Register 8105h From EEPROM Register 8106h From EEPROM Register 8107h From EEPROM Register 8108h From EEPROM Register 8109h From EEPROM Register 810Ah From EEPROM Register 810Bh From EEPROM Register 810Ch From EEPROM Register 810Dh From EEPROM Register 810Eh From EEPROM Register 810Fh From EEPROM Register 8110h From EEPROM Register 8111h From EEPROM Register 8112h From EEPROM Register 8113h From EEPROM Register 8114h From EEPROM Register 8115h From EEPROM Register 8116h From EEPROM Register 8117h From EEPROM Register 8118h From EEPROM Register 8119h From EEPROM Register 811Ah From EEPROM Register 811Bh 41h--Hardwired by manufacturer Xh--Hardwired by Manufacturer XXh--Depends on status of ADM1041 at power-up. XXh--Depends on status of ADM1041 at power-up. XXh--Depends on status of ADM1041 at power-up. Factory EEPROM Value
00h 00h 00h FEh 20h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h XXh - Factory Cal Values XXh - Factory Cal Values XXh - Factory Cal Values XXh - Factory Cal Values 00h 00h 00h 00h
Rev. A | Page 41 of 64
ADM1041 DETAILED REGISTER DESCRIPTIONS
Table 9. Register 00h, Status1. Power-On Default XXh (Refer to the logic schematic--Figure 24.)
Bit No. 7 6 5 4 3 2 1 0 Name ovfault uvfault ocpto mfg1 mfg2 mfg3 mfg4 mfg5 R/W R R R R R R R R Description Overvoltage fault has occurred. Undervoltage fault has occurred. Overcurrent has occured and timed out (ocpf is in Status3). MON1 flag. MON2 flag. MON3 flag. MON4 flag. MON5 flag.
Table 10. Register 01h, Status2. Power-On Default XXh (Refer to the logic schematic--Figure 24.)
Bit No. 7 6 5 4 3 2 1 0 Name Share_OK OrFET_OK REVERSE_OK VDD_OK GND_OK intrefok extrefok vddov R/W R R R R R R R R Description Current share is within limits. ORing MOSFET is on. reverseok--No reverse voltage has occured across the ORing MOSFET. VDD is within limits . Connection of GND pin is good. Internal voltage reference is within limits. External voltage reference is within limits. VDD is above its OV threshold.
Table 11. Register 02h, Status3. Power-On Default XXh (Refer to the logic schematic--Figure 24.)
Bit No. 7 6 5 4 3 2 1 0 Name m_acsns_r m_pson_r m_penok_r m_psonok_r m_DC_OK_r ocpf PULSE_OK fault R/W R R R R R R R R Description Reflects the status on ACSENSE1/ACSENSE2. Reflects the status of PSON. Reflects the status of PEN. Status of PSONLINK. Status of DC_OK. An overcurrent has occured, direct from comparator Pulses are present at the PULSE pin. Fault latch.
Table 12. Register 03h, Calibration Bits. Power-On Default from EEPROM Register 8103h during Power-Up.
Bit No. 7-6 Name rev_volt_off R/W R/W Description Reverse Voltage Detector Turn Off Threshold: b7 b6 Function 0 0 100 mV 0 1 150 mV 1 0 200 mV 1 1 250 mV Reverse Voltage Detector Turn On Threshold: b5 b4 Function 0 0 20 mV 0 1 30 mV 1 0 40 mV 1 1 50 mV Gatepen Option. When set, PEN is gated by acsok. Gateramp Option. When set, soft-start is gated by acsok.
Rev. A | Page 42 of 64
5-4
rev_volt_on
R/W
3 2
gatepen gateramp
R/W R/W
ADM1041
Bit No. 1-0 Name loadov_recover R/W R/W Description b1 0 0 1 1 b0 0 1 0 1 Function Add 100 s delay Add 200 s delay Add 300 s delay Add 400 s delay
Table 13. Register 04h, Current Sense CC. Power-On Default from EEPROM Register 8104h during Power-Up.
Bit No. 7-3 2 1-0 Name curr_limit Share_OK_Window Share_OK_thresh R/W R/W R/W Description This register contains current sense trim level setting at which current limiting starts Share_OK Window Comparator Thresholds b1 b0 Function 0 0 100 mV 0 1 200 mV 1 0 300 mV 1 1 400 mV
Table 14. Register 05h, Current Share Offset. Power-On Default from EEPROM Register 8105h during Power-Up.
Bit No. 7-0 Name ISHARE_offset R/W R/W Description This register contains current share offset trim level. Writing 00h corresponds to the min offset. FFh corresponds to maximum offset. See the Current Limit Error Amplifier section in the Specifications for more information.
Table 15. Register 06h , Current Share Slope. Power-On Default from EEPROM Register 8106h during Power-Up.
Bit No. 7-1 0 Name ISHARE_slope Reserved R/W R/W X Description This register contains current share slope trim level. Don't Care
Table 16. Register 07h, EEPROM_lock. Power-On Default from EEPROM Register 8107h during Power-Up.
Bit No. 7 6 5 4 3 2 1 0 Name Reserved lock6 lock5 lock4 lock3 lock2 lock1 lock0 R/W X R/W R/W R/W R/W R/W R/W R/W Description Don't Care Locks 8140h-817Fh Locks 8120h-813Fh Locks 8100h-811Fh Locks 80C0h-80FFh Locks 8080h-80BFh Locks 8040h-807Fh Locks 8000h-803Fh
Available FRU. ADI cal registers, Locked by manufacturer. ADM1041 Config Boot registers. Available FRU. Available FRU. Available FRU. Available FRU.
Table 17. Register 08h, Load OV Trim. Power-On Default from EEPROM Register 8108h during Power-Up.
Bit No. 7-0 Name load_ov R/W R/W Description Load OV trim
Table 18. Register 09h, Local UVP Trim. Power-On Default from EEPROM Register 8109h during Power-Up.
Bit No. 7-0 Name local_uvp R/W R/W Description Local UVP trim
Rev. A | Page 43 of 64
ADM1041
Table 19. Register 0Ah, Local OVP Trim. Power-On Default from EEPROM Register 810Ah during Power-Up.
Bit No. 7-0 Name local_ovp R/W R/W Description Local OVP Trim
Table 20. Register 0Bh, OTP Trim. Power-On Default from EEPROM Register 810Bh during Power-Up.
Bit No. 7-4 3-1 0 Name otp_trim reserved softotp R/W R/W X R/W Description OTP Threshold Don't Care Configure Soft OTP Option 0 = mon5 +ve ov = ov 1 = mon5 +ve ov = softotp
Table 21. Register 0Ch, ACSENSE Trim. Power-On Default from EEPROM Register 810Ch during Power-Up.
Bit No. 7-3 2-0 Name acsns_thresh acsns_hyst R/W R/W R/W Description ACSENSE Threshold Trim Settings ACSENSE Hysteresis Trim Settings
Table 22. Register 0Dh, Config1. Power-On Default from EEPROM Register 810Dh during Power-Up.
Bit No. 7 6 5 4 Name up_pson_m reserved reserved uvbm R/W R/W
X X
R/W
3-1
mn1s2, mn1s1, mn1s0
R/W
Description 0 = internal PSON. 1 = support via SMBus. Selects PSON from config6 < 1 > = m_pson_w. Don't Care. Don't Care. Undervoltage Blanking Mode. uvbm = 1: blanking-hold period starts from recovery of AC_OK. uvbm = 0: blanking-hold period starts following SCL = 0 while i2cm = 1. b3 b2 b1 option mfg1 ov iopin = ACSNS1 iopin = ACSNS1 +ve ov iopin < 1.15 V iopin > 1.25 V 0 1 1 +ve uv iopin < 1.25 V iopin > 1.35 V 1 0 0 -ve ov iopin < 1.25 V iopin > 1.35 V 1 0 1 -ve uv iopin < 1.15 V iopin > 1.25 V 1 1 0 flag iopin < 1.15 V iopin > 1.25 V 1 1 1 flag iopin < 1.15 V iopin > 1.25 V 0 = pins are configured as SDA/SCL (default). 1 = SCL pin is configured as AC_OKLink output. SDA pin is configured as PSONLINK output. 0 0 0 0 0 1 0 1 0
uv (true = high) (true = high)
0 1 0 1 0 1 0 1 0 1 1 0
0 1 0 0 1 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 0 0 0
0
i2cmb
R/W
Rev. A | Page 44 of 64
ADM1041
Table 23. Register 0Eh, Config2. Power-On Default from EEPROM Register 810Eh during Power-Up.
Bit No. 7-5 Name mn2s2, mn2s1, mn2s0 R/W W Description b7 0 0 0 0 1 1 1 1 b6 0 0 1 1 0 0 1 1 b5 0 1 0 1 0 1 0 1 option iopin = ACSENSE2 iopin = ACSENSE2 +ve ov iopin < 1.15 V iopin > 1.25 V +ve uv iopin < 1.25 V iopin > 1.35 V -ve ov iopin < 1.25 V iopin > 1.35 V -ve uv iopin < 1.15 V iopin > 1.25 V flag iopin < 1.15 V iopin > 1.25 V flag iopin > 1.25 V iopin > 1.25 V option iopin = PSON iopin = PSON +ve ov iopin < 1.15 V iopin > 1.25 V +ve uv iopin < 1.25 V iopin > 1.35 V -ve ov iopin < 1.25 V iopin > 1.35 V -ve uv iopin < 1.15 V iopin > 1.25 V flag iopin < 1.15 V iopin > 1.25 V flag iopin < 1.15 V iopin > 1.25 V option 400 ms 200 ms 800 ms 1600 ms mfg2
Ov uv
(true = high) (true = high) 0 1 0 1 0 1 0 1 0 1 1 0 mfg3 0 1 0 0 1 0 0 0 0 0 0 0
ov
0 0 1 0 0 0 0 1 0 0 0 0
uv
4-2
mn3s2, mn3s1, mn3s0
R/W
b4 0 0 0 0 1 1 1 1
b3 0 0 1 1 0 0 1 1
b2 0 1 0 1 0 1 0 1
(true = low) (true = high) 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
1-0
pokts1, pokts0
R/W
DC_OKon_delay
b1 0 0 1 1
b0 0 1 0 1
Rev. A | Page 45 of 64
ADM1041
Table 24. Register 0Fh, Config3. Power-On Default from EEPROM Register 810Fh during Power-Up.
Bit No. 7-5 Name mn4s2, mn4s1, mn4s0 R/W R/W Description b7 b6 b5 0 0 0 option iopin = DC_OK mfg4 ov
uv
Refer to the Configuration table (Table 45) 0 1 0 1 0 1 0 1 0 1 0 0 mfg5 0 1 0 0 1 0 0 0 0 0 0 0 ov 0 0 1 0 0 0 0 1 0 0 0 0 uv
0 0 0 1 1 1 1 4-2 mn5s2, mn5s1, mn5s0 R/W b4
0 1 1 0 0 1 1 b3
1 0 1 0 1 0 1 b2
iopin = DC_OK +ve ov iopin < 1.15 V iopin > 1.25 V +ve uv iopin < 1.25 V iopin > 1.35 V -ve ov iopin < 1.25 V iopin > 1.35 V -ve uv iopin < 1.15 V iopin > 1.25 V flag iopin < 1.15 V iopin > 1.25 V flag iopin < 1.15 V iopin > 1.25 V option
Refer to the Configuration table (Table 45)
1-0
psonts1, psonts0
R/W
iopin = AC_OK iopin = AC_OK +ve ov iopin < vdac iopin > vdac 0 1 1 +ve uv iopin < vdac iopin > vdac 1 0 0 -ve ov iopin < vdac iopin > vdac 1 0 1 -ve uv iopin < vdac iopin > vdac 1 1 0 flag iopin < vdac iopin > vdac 1 1 1 vref out (e.g., 2.5 V VREF PSON debounce time: b1 b0 option 0 0 80 ms 1 0 0 ms (no debounce) 1 0 40 ms 1 1 160 ms
0 0 0
0 0 1
0 1 0
0 1 0 1 0
1
0 1 0 0 1
0
0 0 1 0 0
0
0 1 0 1
0 0 0 0
0 1 0 0
Table 25. Register 10h, Config4. Power-On Default from EEPROM Register 8110h during Power-Up.
Bit No. 7-6 Name DC_OKoff_delay R/W R/W Description DC_OKoff delay (Power-Off Warn Delay) b7 b6 option 0 0 2 ms 0 1 0 ms 1 0 1 ms 1 1 4 ms b5 b4 option 0 0 1%
5-4
ISHARE_capture
R/W
Rev. A | Page 46 of 64
ADM1041
Bit No. Name R/W Description 0 1 2% 1 0 3% 1 1 4% Soft-Start Step b3 b2 Rise Time 0 0 300 s 0 1 10 ms 1 0 20 ms 1 1 40 ms EEPROM programmable second address bit. When this bit is set, the trim registers including this register are not writable via SMBus. To make registers writable again, the trim-lock bit in the EEPROM must first be erased and the value downloaded using either power-up or test download.
3-2
ssrs1, ssrs0
R/W
1 0
add1 trim_lock
R/W R/W
Table 26. Register 11h, Config5. Power-On Default from EEPROM Register 8111h 8110h during Power-Up.
Bit No. 7 6 5 4-3 2 1 0 Name curr_lim_dis polpen0 polcbd0 Reserved ocpts2 gndok_dis cbdlm R/W R/W R/W R/W X R/W R/W R/W Description Mask effect of OCP to general logic (status flag still gets asserted) when curr_lim_dis = 1. Sets polarity of PEN output. Refer to the Configuration table (Table 45). Sets polarity of CBD output. Refer to the Configuration table (Table 45). Don't Care. Set this bit to 1 when 0 OCP ridethrough is required. A small delay still exists. Refer to Reg 12h and the Configuration table (Table 45). Disable gndok input to power management debounce logic. Select CBD latch mode. 0 = nonlatching; 1 = latching.
Table 27. Register 12h, Config6. Power-On Default from EEPROM Register 8112h 8110h during Power-Up.
Bit No. 7 Name rsm R/W R/W Description Restart Mode. When rsm = 1, the circuit attempts to restart the supply after an undervoltage or overcurrent at about 1 second intervals. Latch Mode. When rsm = 0, UV and OC faults latch the output off. Cycling PSON or removing the supply to the IC is then required to reset the latch and permit a restart. Configure microprocessor to control/gate signal from acinok to acsok. 0 = standalone. 1 = microprocessor support mode. Microcessor control of acsok (ACSENSE). OCP Ridethrough (Reg 11h[2] = 0) OCP Ridethrough (Reg11h[2] = 1) b4 b3 Period b4 b3 Period 0 0 1 second 0 0 128 s 0 1 2 seconds 0 1 256 s 1 0 3 seconds 1 0 384 s 1 1 4 seconds 1 1 512 s AC Sense Mode. 0 means AC_OK is derived from ACSENSE1, whereas 1 means AC_OK is derived from ACSENSE2. Microprocessor control of pson. 0 = 75%. Set current share clamp release threshold. 1 = 88%.
6
up_AC_OK_m
R/W
5 4-3
m_acsns_w ocpts1, ocpts0
(W) R/W
2 1 0
acss m_pson_w ISHARE_clamp
(W) (W) R/W
Table 28. Register 13h, Config7. Power-On Default from EEPROM Register 8113h during Power-Up.
Bit No. Name R/W Description
Rev. A | Page 47 of 64
ADM1041
Bit No. 7 6 5 4 3 2 1 0 Name polpen1 polcbd1 polDC_OK1 polAC_OK1 polfg m_shr_clmp m_cbd_w m_cbd_clr R/W R/W R/W R/W R/W R/W (W) R/W R/W Description Sets polarity of PEN output. Refer to the Configuration table (Table 45). Sets polarity of CBD output. Refer to the Configuration table (Table 45). Sets polarity of DC_OK output. Refer to the Configuration table (Table 45). Sets polarity of AC_OK output. Refer to the Configuration table (Table 45). Sets polarity of OrFET gate control: 0 = inverted (low = on). Allow the microprocessor to directly control the share clamp 0 = normal share clamp operation, i.e., not clamped 1 = assert share clamp, i.e., clamped. Allow the microprocessor to write directly to CBD as a possible way of adding an additional port. This might be a blinking led or a fail signal to the system. Microprocessor clear of CBD latch (if configured as latching) folowing an SMBAlert.
Table 29. Register 14h, Current Sense Divider Error Trim 1. Power-On Default from EEPROM Register 8114h during Power-Up.
Bit No. 7-0 Name os_div R/W R/W Description Trim-out offset due to external resistor divider tolerances (for common-mode correction).
Table 30. Register 15h, Current Sense Amp Offset Trim 2. Power-On Default from EEPROM Register 8115h during Power-Up.
Bit No. 7-0 Name os_dc R/W R/W Description Trim-out current sense amplifier offset (dc offset correction).
Table 31. Register 16h, Current Sense Options 1. Power-On Default from EEPROM Register 8116h during Power-Up.
Bit No. 7-6 5-3 Name isense3 os_div_range R/W R/W R/W Description Unused. External Divider Tolerance Trim Range (Common-Mode Trim Range). b5 b4 b3 Range External Resistor Tolerance 0 0 0 -5 mV -0.25% 0 0 1 -10 mV -0.50% 0 1 0 -20 mV -1.00% 1 0 0 +5 mV +0.25% 1 0 1 +10 mV +0.50% 1 1 0 +20 mV +1.00% Gain Selector b2 b1 b0 Gain Range 0 0 0 65x 34.0 mV to 44.5 mV 0 0 1 85x 26.0 mV to 34.0 mV 0 1 0 110x 20.0 mV to 26.0 mV 1 0 0 135x 16.0 mV to 20.0 mV 1 0 1 175x 12.0 mV to 16.0 mV 1 1 0 230x 9.5 mV to 12.0 mV
2-0
isense_range
R/W
Rev. A | Page 48 of 64
ADM1041
Table 32. Register 17h, Current Sense Option 2. Power-On Default from EEPROM Register 8117h during Power-Up.
Bit No. 7 6 5 Name csense_mode chopper ct_range R/W R/W R/W R/W Description 0 = DIFFSENSE (current sense with external resistor). 1 = CTSENSE (current transformer). When chopper = 1, current sense amplifier is configured as a chopper. Otherwise, current sense amplifier is continuous time. Gain Range 0 = 4.5 0.45 V-0.68 V 1 = 2.57 0.79 V-1.20 V 0: ground offset = 100 mV; ISHARE error amp, offset = 50 mV. 1: ground offset = 0; ISHARE error amp offset = 0. Don't Care. Internal Sense Amp Offset Trim Range for Differential Current Sense b2 b1 b0 Range 0 0 0 -8 mV 0 0 1 -15 mV 0 1 0 -30 mV 1 0 0 +8 mV 1 0 1 +15 mV 1 1 0 +30 mV
4 3 2-0
select_gnd_offset Reserved os_dc_range
R/W X R/W
Gain -1 -2 -4 +1 +2 +4
Table 33. Register 18h, UV Clamp Trim. Power-On Default from EEPROM Register 8118h during Power-Up.
Bit No. 7-0 Name uv_clamp R/W R/W Description This register contains the false UV clamp settings.
Table 34. Register 19h, Load Voltage Trim. Power-On Default from EEPROM Register 8119h during Power-Up.
Bit No. 7-0 Name load_v R/W R/W Description This register contains the set load voltage trim settings.
Table 35. Register 1Ah, Sel CBD/SMBAlert1. Power-On Default From EEPROM Register 811Ah during Power-Up.
Bit No. 7 6 5 4 3 2 1 0 Name selcbd1 <7> selcbd1 <6> selcbd1 <5> selcbd1 <4> selcbd1 <3> selcbd1 <2> selcbd1 <1> Selcbd1 <0> R/W R/W R/W R/W R/W R/W R/W R/W R/W Description ovfault uvfault ocpto (ridethrough timed out, ocpf flag) acsnsb (inverted) ocpf otp (MON5 OV) orfetokb (inverted) Share_OKb (inverted)
Rev. A | Page 49 of 64
ADM1041
Table 36. Register 1Bh, Sel CBD/SMBAlert2. Power-On Default from EEPROM Register 811Bh during Power-Up.
Bit No. 7 6 5 4 3 2 1 0 Name selcbd2 <7> selcbd2 <6> selcbd2 <5> selcbd2 <4> selcbd2 <3> selcbd2 <2> selcbd2 <1> selcbd2 <0> R/W R/W R/W R/W R/W R/W R/W R/W R/W Description VDDOK b (inverted) mfg1 mfg2 mfg3 mfg4 m_cbd_w Microprocessor Control of CBD mfg5 Not used.
Table 37. Register 1Ch, Manufacturer's ID. Power-On Default 41h.
Bit No. 7-0 Name Manufacturer's ID Code R/W R Description This register contains the manufacturer's ID code for the device. It is used by the manufacturer for test purposes and should not be read from or written to in normal operation.
Table 38. Register 1Dh, Revision Register. Power-On Default 01h.
Bit No. 7-4 3-0 Name Major Revision Code Minor Revision Code R/W R R Description These 4 bits denote the generation of the device. These 4 bits contain the manufacturer's code for minor revisions to the device. Rev 0 = 0h, Rev 1 = 1h, and so on. This register is used by the manufacturer for test purposes. It should not be read from or written to in normal operation.
Table 39. Register 2Ah, Status1 Mirror. Power-On Default 00h. These flags are cleared by a register read, provided the fault no longer persists.
Bit No. 7 6 5 4 3 2 1 0 Name ovfault_L uvfault_L ocpto_L mfg1_L mfg2_L mfg3_L mfg4_L mfg5_L R/W R R R R R R R R Description Overvoltage fault has occurred. Undervoltage fault has occurred. Overcurrent has occured and timed out (ocpf is in Status3). MON1 flag. MON2 flag. MON3 flag. MON4 flag. MON5 flag. Note that latched bits are clocked on a low-to-high transmission only. Also note that these register bits are cleared when read via the SMBus, except if the fault is still present. It is recommended to read the register again after the faults disappear to ensure reset.
Rev. A | Page 50 of 64
ADM1041
Table 40. Register 2Bh, Status2 Mirror. Power-On Default 00h. These flags are cleared by a register read, provided the fault no longer persists.
Bit No. 7 6 5 4 3 2 1 0 Name Share_OKb_L orfetokb_L reverseokb_L VDDOK b_L gndokb_L intrefokb_L extrefokb_L vddov_L R/W R R R R R R R R Description share fault ORFET fault reverse fault vdd fault gnd fault intref fault extref fault vddov Note that latched bits are clocked on a low-to-high transmission only. Also note that these register bits are cleared when read via the SMBus, except if the fault is still present. It is recommended to read the register again after faults disappear to ensure reset.
Table 41. Register 2Ch, Status3 Mirror. Power-On Default 00h These flags are cleared by a register read, provided the fault no longer persists.
Bit No. 7 6 5 4 3 2 1 0 Name m_acsns_rb_L m_pson_rb_L m_penok_rb_L m_psonok_rb_L m_DC_OK_rb_L ocpf PULSE_OKb_L fault R/W R R R R R R R R Description AC_OK fault PSON fault PEN fault PSONLINK fault DC_OK fault ocpf fault pulse fault fault latch Note that latched bits are clocked on a low-to-high transmission only. Also note that these register bits are cleared when read via the SMBus, except if the fault is still present. It is recommended to read the register again after the faults disappear to ensure reset.
MANUFACTURING DATA
Table 42.
Register 81F0h Register 81F1h Register 81F2h Register 81F3h Register 81F4h Register 81F5h Register 81F6h Register 81F7h Register 81F8h Register 81F9h Register 81FAh Register 81FBh Register 81FCh Register 81FDh Register 81FEh Register 81FFh PROBE1_BIN PROBE2_BIN FT_BIN PROBE1_CHKSUM PROBE2_CHKSUM FT_CHKSUM QUAL_PART_ID Probe 1 cell current data (integer) Probe 1 cell current data (two decimal places) Probe 2 cell current data (integer) Probe 2 cell current data (two decimal places) Final test cell current data (integer) Final test cell current data (two decimal places) Probe X coordinate Probe Y coordinate Wafer number
Rev. A | Page 51 of 64
ADM1041 MICROPROCESSOR SUPPORT
Table 43.
Mnemonic m_pson_r m_pson_w Description Allows the microprocessor to read the state of PSON. This allows only one ADM1041 to be configured as the PSON interface to the host system. Allow the microprocessor to write to control the PSON function of each ASIC. When in microprocessor support mode, the principle configuration for controlling power-on/power-off will be as follows: One ADM1041 would be configured to be the interface to the host system through the standard PSON pin. This pin would be configured not to write through to the PSON debounce block. The microprocessor would poll the status of this ADM1041 by reading m_pson_r. Debouncing would be done by the microprocessor. If m_pson_r changed state, the microprocessor would write the new state to m_pson_w in all ADM1041s on the SMBus. If a fault were to occur on any output, the SMBAlert interrupt would request microprocessor attention. If this means turning all ADM1041s off, this would be done by writing a zero to the m_pson_w bit. Allows the microprocessor to read the state of ACSENSE1/ACSENSE2. This allows one ADM1041 to be configured as the interface to the host power supply. Allow the microprocessor to write to control the ACSOK function of each ADM1041. When in microprocessor support mode the principle configuration for controlling AC_OK, undervoltage blanking, PEN gating, and RAMP/SS gating will be as follows: One ADM1041 will be configured to be the interface with the host power supply AC monitoring circuitry. This ADM1041 might be configured so that the acsns signal would be written through or would not be written through. Regardless, the microprocessor would monitor m_acsns_r and write to m_acsns_w as appropriate. Since it is possible to sense but not to write through, it is possible to configure a second ADM1041 to monitor a second ac or bulk voltage. Allow the P to write directly to m_shr_clmp to control when the ISHARE clamp is released. During a hot-swap insertion, there may be a need to delay the release of the ISHARE clamp. This allows the designer an option over the default release at 75% or 88% of the reference ramp (soft-start). Allow the microprocessor to write directly to CBD as a possible way of adding an additional output port. This might be for blinking LEDs or as a FAIL signal to the system. Allows the microprocessor to clear the CBD latch following an SMBalert. If CBD is configured to be latching, there may be circumstances that lead to CBD/SMBAlert being set by, for example, one of the MON flags but does not lead to PSON being cycled and CBD being reset. In this case, the microprocessor needs to write directly to CBD to reset the latch. This flag indicates the status of the MON5 pin. This flag indicates the status of the MON4 pin. This flag indicates the status of the MON3 pin. This flag indicates the status of the MON2 pin. This flag indicates the status of the MON1 pin. If this flag is high, an overcurrent has occurred and timed out. If this flag is high, an undervoltage has been sensed If this flag is high, an overvoltage has been sensed. If this flag is high, a VDD overvoltage has been sensed. If this flag is low, the externally available reference on Pin 18 is overloaded. If this flag is low, the internal reference has no integrity. If this flag is low, the ASIC ground, Pin 7, is open either pin to PCB or bond wires. If this flag is low, VDD is below its UVL or the power mangement block has a problem, a reference voltage, ground fault, or VDD overvoltage fault. If this flag is low, the OrFET has an excessive reverse voltage. If this flag is low, either PULSE_OK, penok, loadvok, or reverseok is false. If this flag is low, the current share accuracy is out of limits. Fault latch. If this flag is high, either an ovfault, uvfault, or ocp has occured. Pulses are present at ACSENSE 1.
Rev. A | Page 52 of 64
Register 02h 12h
Bit 6 1
Read/Write Read-only Write-only
m_acsns_r m_acsns_w
02h 12h
7 5
Read-only Write-only
m_shr_clmp
13h
2
Write-only
m_cbd_w
1Bh
1
Write-only
m_cbd_clr
13h
0
Write-only
mfg5 mfg4 mfg3 mfg2 mfg1 ocpto uvfault ovfault vddov extrefok intrefok gndok VDDOK reverseok orfetok Share_OK fault PULSE_OK
00h 00h 00h 00h 00h 00h 00h 00h 01h 01h 01h 01h 01h 01h 01h 01h 02h 02h
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1
Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only read only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only
ADM1041
Mnemonic ocpf m_DC_OK_r m_psonok_r m_penok_r m_pson_r m_acsns_r mfg5_L mfg4_L mfg3_L mfg2_L mfgl_L ocpto_L uvfault_L ovfault_L vddov_L extrefokb_L intrefokb_L gndokb_L VDDOK b_L reverseokb_L orfetokb_L Share_OKb_L fault_L PULSE_OKb_L ocpf_L m_DC_OK_rb_L m_psonok_rb_L m_penok_rb_L m_pson_rb_L m_acsns_rb_L Description If this flag is high, an overcurrent has been sensed and the ocp timer has started. This flag indicates the status of the DC_OK pin. This flag indicates the status of the PSONLINK pin. This flag indicates the status of the PEN pin. This flag indicates the status of the PSON pin. This flag indicates the status of the ACSENSE1/ACSENSE2 pin. Latched status of MON5 flag. Latched status of MON4 flag. Latched status of MON3 flag. Latched status of MON2 flag. Latched status of MON1 flag. Latched ocpto. Latched uvfault. Latched ovfault. Latched vddov fault. Latched extref fault. Latched intref fault. Latched gnd fault. Latched VDD fault. Latched reverse voltage fault. Latched orfet fault. Latched share fault. Latched fault. Latched pulse fault. Latched ocpf fault. Latched DC_OK fault. Latched PSONLINKfault. Latched PEN fault. Latched PSON fault. Latched ACSENSE fault. Register 02h 02h 02h 02h 02h 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Bh 2Bh 2Bh 2Bh 2Bh 2Bh 2Bh 2Bh 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch Bit 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Read/Write Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only
Notes to Microprocessor (P) support. 1. Possible ways to turn the ADM1041 on or off in response to a system request or a fault include: * * * 2. Daisy chaining other ADM1041 PSON pins to the PEN pin, which is controlled by PSON on one ADM1041. The microprocessor looks after the PSON--system interface and any shutdowns due to faults. Connect all AC_OKLink pins together and connect all PSONLINK pins together. These pins must be configured appropriately.
Flags appended with _L are latched (Registers 2Ah/2Bh/2Ch). The latch is reset when the flag is read, except when the fault is still present. It is advisable to continue reading the flag(s) until the fault(s) have cleared.
Rev. A | Page 53 of 64
ADM1041 TRIM TABLE
This table shows all of the trims that can be set in the ADM1041. Table 44.
Description Set Load Voltage. Trim output from differential amplifier to set voltage at load. Set Load OV. Trim calibrated output from remote sense amplifier to set load OV threshold. Set False UV Clamp Threshold. Fine trim output to set voltage before OR-FET in case of load OV (at input pins). Set Local UVP Threshold. Fine trim output from local sense buffer to set UVP threshold (at input pins). Set Local OVP Threshold. Fine trim output from sense buffer to set OVP threshold (at input pins). External Divider Offset Trim Range. Name load_v load_ov Range 1.7 V-2.3 V (at input pins) 105%-120% Offset input 1.3 V-2.1 V Steps 255 255 Step Size 1.74 mV-3.18 mV 1.6 mV Reg 19h 08h Bit No. 7-0 7-0
uv_clamp
255
1.94 mV-5.07 mV
18h
7-0
local_uvp
1.3 V-2.1V
255
1.94 mV-5.07 mV
09h
7-0
local_ovp
1.9 V-2.85 V
255
2.48 mV-5.59 mV
0Ah
7-0
os_
div_range
5 mV 10 mV 20 mV 255
20 V 39 V 78 V
16h
5-3
External Divider Offset Trim. Trim out offset due to resistor divider tolerances. DC Offset Trim Range.
os_div os_dc_range 8 mV 15 mV 30 mV
14h 30 V 60 V 120 V 17h
7-0 3-0
Current Sense DC Offset Trim. Trim out amplifier dc offset. Calibrate Current Sense Range. Differential sense input, six ranges configurable.
os_dc ISENSE_range 9.5 to 12.0 mV 12.0 to 16.0 mV 16.0 to 20.0 mV 20.0 to 26.0 mV 26.0 to 34.0 mV 34.0 to 44.5 mV 0.45 to 0.68 V 0.79 to 1.2 V
255
15h 16h
7-0 2-0
Current Transformer Gain Range. Calibrate Current Sense. ISHARE = 2.0 V. Current Share Offset. Trim offset to be added to ISHARE output. Current Limit Trim. Current sense level where current limiting will start. OTP Sense Threshold. Set AC Sense Threshold. Set AC Sense Hysteresis.
ct_range ISHARE_slope ISHARE_offset curr_limit otp_trim (at input pins) acsns_thresh acsns_hyst
17h 127 8 mV (at SHRO) 5.5 mV 26 mV (at SHRO) 27 mV 14 mV 50 mV 06h 05h 04h 0Bh 0Ch 0Ch
5 7-1 7-0 7-3 7-4 7-3 2-0
0 to 1.25 V (at SHRO) 105%-130% (SHRO 2.1 V-2.6 V) 2.1 V-2.5 V 1.10 V-1.45 V 200 mV-550 mV
255 31 15 31 7
Rev. A | Page 54 of 64
ADM1041 APPENDIX A--CONFIGURATION TABLE
This table is included for users to program the part by function, rather than by register. Table 45.
Description Chip address is 1010xxx. Second address bit (EEPROM programmable). Bit No. Name Bit Bit Bit Option Target device 0 1 4
1
add1
b1 0 0 0
ADD0 L H Z
xxx 000 001 100
First address bit: ADD0 = L, pin to ground. ADD0 = H, pin to VDD. ADD0 = Z, pin open. Broadcast address. Config AC_OKLink and PSONLink.
1 1 1 X 0 i2cmb b0 0 1 b6 0 1 b7 0 1 b4 0 1
L H Z X
010 011 101 111
2 3 5 ALL
Configure ACSENSE to be hardware derived or from an SMBus command. Configure PSON to be hardware derived or from an SMBus command. Configure UV blanking to be internally derived or from AC_OKLink. (Set opposite to i2cmb). Build FAULT or SMBAIert signal. Allows a composite interrupt to be constructed by ORing up to 15 different signals.
6
up_AC_OK_m
7
up_pson_m
4
uvbm
Mode Normal SMBus, microprocessor SCL = AC_OK Link SDA = PSON Link Mode Hardware ACSENSE Microprocessor support via SMBus Mode Hardware PS_ON Micorporcessor support via SMBus Mode UVB follows AC_OKLink UVB follows ACSENSE
7-0
selcbd1
This uses the CBD pin. m_cbd_w is a P writable bit. 7-1 selcbd2
bn 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
signal ovfault uvfault ocpt0 (ridethough timed out) acsnsb ocpf otp (mov5) orfetokb Share_OKb VDDOK b mfgl mfg2 mfg3 mfg4 m_cbd_w mfg5 Not used
Rev. A | Page 55 of 64
ADM1041
Description Trim registers, locking bit. Bit No. 0 Name trim_lock Bit Bit Bit b0 0 1 b7 0 1 b6 0 1 Current sense dc offset adjustment (with respect to the input). Option Mode Trimming mode All trim registers locked out Mode Differential sense CT Sense Mode Differential current sense amplifier is continuous (recomended) Differential sense amplifier is chopper Trim
Current Sense Mode.
7
csense_mode
Chopper Mode.
6
chopper
2-0
os_dc_range
Compensates for the amplifier input offset voltage.
b5 0 0 0
b4 0 0 1
b3 0 1 0
-8 mV -15 V -30 V
1 1 1 Current sense external divider error correction range (with respect to the input). Compensates for the mismatch error of the external resistor dividers at Pins 2 and 3. Set differential current sense gain. 5-3 os_div_range b5 0 0 0 1 1 1 2-0 diff_gain b2 0 0 0 1 1 1
0 0 1 b4 0 0 1 0 0 1 b1 0 0 1 0 0 1
0 1 0 b3 0 1 0 0 1 0 b0 0 1 0 0 1 0 b5 0 1 b7 0 1
+8 mV +15 mV +30 mV Trim -5 mV -10 mV -20 mV +5 mV +10 mV +20 mV Gain 65 85 110 135 175 230 Gain 4.5 2.57 Range 34.0 mV-44.5 mV 26.0 mV-34.0 mV 20.0 mV-26 mV 16.0 mV-20.0 mV 12.0 mV-16.0 mV 9.8 mV-12.0 mV Range 0.45 V-0.68 V 0.79 V-1.20 V
Set current transformer input gain.
5
ct_range
OCP mode. Disables OCP shutdown.
7
curr_lim_dis
Mode OCP timer starts when CCMP > 0.5 V No OCP shutdown Period 1s 2s 3s 4s 100 ms
OCP Ride Through. Sets the OCP timer duration before OCP shutdown occurs.
4-3
ocpts1 Reg12h ocpts0 Reg12h
2
ocpts2
b4 0 0 1 1 X
b3 0 1 0 1 X
Rev. A | Page 56 of 64
ADM1041
Description Option: Pulse/ACSENSE1/MON1. Bit No. 3-1 Name mn1s2 mn1s1 mnls0 Bit b3 0 0 0 0 1 1 1 1 Option: ACSENSE2/MON 7-5 mn2s2 mn2s1 mn2s0 b7 0 0 0 0 1 1 1 1 Option: PSON/MON3 4-2 mn3s2 mn3s1 mn3s0 b4 0 0 0 0 1 1 1 1 Option: DC_OK/MON4 7-5 mn4s2 mn4s1 mn4s0 b7 0 0 b6 0 0 b5 0 1 flag iopin = DC_OK iopin = DC_OK ov uv b6 0 0 1 1 0 0 1 1 b3 0 0 1 1 0 0 1 1 b5 0 1 0 1 0 1 0 1 b2 0 1 0 1 0 1 0 1 flag iopin = ACSENSE2 iopin = ACSENSE2 +ve ov iopin < 1.15 V +ve ov iopin > 1.25 V +ve uv iopin < 1.25 V +ve uv iopin > 1.35 V -ve ov iopin < 1.25 V -ve ov iopin > 1.35 V -ve uv iopin < 1.15 V -ve uv iopin > 1.25 V flag iopin < 1.15 V flag iopin > 1.25V flag iopin < 1.15V flag iopin > 1.25 V iopin = PSON on = low iopin = PSON on = high +ve ov iopin < 1.15 V +ve ov iopin > 1.25 V +ve uv iopin < 1.25 V +ve uv iopin > 1.35 V -ve ov iopin < 1.25 V -ve ov iopin > 1.35 V -ve uv iopin < 1.15 V -ve uv iopin > 1.25 V flag iopin < 1.15 V flag iopin > 1.25 V flag iopin < 1.15 V flag iopin > 1.25 V ov uv Bit b2 0 0 1 1 0 0 1 1 Bit b1 0 1 0 1 0 1 0 1 Option flag iopin = ACSENSE1 iopin = ACSENSE1 +ve ov iopin < 1.15 V +ve ov iopin > 1.25 V +ve uv iopin < 1.25 V +ve uv iopin > 1.35 V -ve ov iopin < 1.25 V -ve ov iopin > 1.35 V -ve uv iopin < 1.15 V -ve uv iopin > 1.25 V flag iopin < 1.15 V flag iopin > 1.25 V flag iopin < 1.15 V flag iopin > 1.25 V ov uv
0 1 0 0 1 0 1 0 1 1
0 1 0 1 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0
0 1 0 1 0 1 0 1 0 1 1 0 flag
0 1 0 0 1 0 0 0 0 0 0 0 ov
0 0 1 0 0 0 0 1 0 0 0 0 uv
0 1 0 1 0 1 0 1 0 1 1 0
0 1 0 0 1 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 0 0 0
Rev. A | Page 57 of 64
ADM1041
Description To set DC_OK polarity, see polDC_OK. Bit No. Name Bit 0 0 1 1 1 1 Option: VREF/AC_OK/MON5. 4-2 mn5s2 mn5s1 mn5s0 b4 0 0 0 0 0 1 1 1 1 AC sense source. 2 acss Bit 1 1 0 0 1 1 b3 0 0 1 1 1 0 0 1 1 Bit 0 1 0 1 0 1 b2 0 1 0 0 1 0 1 0 1 b2 0 1 b2 0 1 0 1 b0 0 1 0 1 b6 0 1 0 1 Option +ve ov iopin < 1.15 V +ve ov iopin > 1.25 V +ve uv iopin < 1.25 V +ve uv iopin > 1.35 V -ve ov iopin < 1.25 V -ve ov iopin > 1.35 V -ve uv iopin < 1.15 V -ve uv iopin > 1.25 V flag iopin < 1.15 V flag iopin > 1.25 V flag iopin < 1.15 V flag iopin > 1.25 V iopin = AC_OK iopin = AC_OK iopin = AC_OK 0 +ve ov iopin < vdac +ve ov iopin > vdac +ve uv iopin < vdac +ve uv iopin > vdac -ve ov iopin < vdac -ve ov iopin > vdac -ve uv iopin < vdac -ve uv iopin > vdac flag iopin < vdac flag iopin > vdac 2.5 V ref out Source AC_OK from ACSENSE1 AC_OK from ACSENSE2 Period 80 ms 0 ms 40 ms 160 ms Period 400 ms 200 ms 800 ms 1600 ms period 2 ms 0 ms 1 ms 4 ms 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 0 flag 0 1 0 0 1 0 0 0 0 0 0 0 ov 0 0 1 0 0 0 0 1 0 0 0 0 uv
To set AC_OK polarity, see polDC_OK.
PSON delay/debounce time.
1-0
psonts1 psonts0
DC_OK on delay. Delay time from dc outputs being enabled to DC_OK being asserted. DC_OK off delay. Delay time from PSON forcingDC_OK to be deasserted to PEN being deasserted.
1-0
pokts1 pokts0
7-6
pots1 pots0
b1 0 0 1 1 b1 0 0 1 1 b7 0 0 1 1
Rev. A | Page 58 of 64
ADM1041
Description Current share capture range. Maximum output voltage control range due to the current share action. Soft-start mode provides option for soft-startramp to be gated by acsnsok Soft-start step rise time (output rise time) Bit No. 5-4 Name ISHARE_capture Bit b5 0 0 1 1 2 gateramp Bit Bit b4 0 1 0 1 b2 0 1 b2 0 1 0 1 b3 0 1 b0 0 1 0 1 b6 0 1 0 1 b4 0 1 0 1 b0 0 1 0 1 b7 0 1 Option Range 1% 2% 3% 4% Mode Soft-start gated by pen only Soft-start gated by acsnsok and pen Rise time 300 s 10 ms 20 ms 40 ms Mode PEN not gated PEN gated by acsnsok Period 100 s 200 s 300 s 400 s Threshold 100 mV 150 mV 200 mV 250 mV Threshold 20 mV 30 mV 40 mV 50 mV Threshold voltage 5% 100 mV 10% 200 mV 15% 300 mV 20% 400 mV Mode OV, UV, OC faults latch Auto-restarts after OCP or undervoltage
3-2
ssrsl ssrs0
b3 0 0 1 1
PEN start-up mode Provides option for PEN to be gated by acsnsok. Load overvoltage debounce
3
gatepen
1-0
loadov_recover
OrFET Reverse Voltage Threshold. Reverse voltage at which the ORFET turns off. OrFET Forward Voltage Threshold Reverse voltage at which the OrFET turns on Share_OK Window Threshold
7-6
rev_volt_off
5-4
rev_volt_on
1-0
Share_OK_thresh
b1 0 0 1 1 b7 0 0 1 1 b5 0 0 1 1 b1 0 0 1 1
Restart Mode Provides an option to autorestart after approximately 1 sec. This applies only to UVP and OCP faults not to OVP faults. Set PEN Output Polarity. Also selects open-drain N-channel or P-channel.
7
rsm
6 7
polpen0 polpen1
b7
b6 FET option N P P N Polarity - + - +
0 0 1 1
0 1 0 1
Rev. A | Page 59 of 64
ADM1041
Description Set CBD Output Polarity Bit No. 5 6 Name polcbd0 polcbd1 Bit Bit b6 0 0 1 1 Bit b5 0 1 0 1 b3 0 1 b5 0 1 0 1 b0 0 1 b0 0 1 b0 0 1 b2 Option FET option N P P N Polarity Polarity - + - +
Set OrFET Gate Drive Polarity This is an open-drain N-FET Set DC_OK Output Polarity. Also selects open-drain N-channel or P-channel.
3
polfg
5 5
mn4s0 polDC_OK
b5 0 0 1 1
Set ISHARE Clamp Release threshold. Percent of nominal output voltage. Configure Soft OTP Option
0
ISHARE_clamp
0
softotp
Select CBD Latch Mode
0
cbdlm
True = low (N-FET on) True = high (N-FET off) FET option Polarity N + P - P - N + Soft-start threshold % 75 88 Mode MON5 OV causes shutdown. MON5 OV turns off and then restarts when temperature falls. Mode cbdlm = nonlatching cbdlm = latching
Set AC_OK Output Polarity Also selects open-drain N-channel or P-channel
2 4
mn5s0 polAC_OK
b4
0 0 1 1 Lock EEPROM Contents 7-0 eeprom_locks lock7 lock6 lock5 lock4 lock3 lock2 lock1 lock0 selects_gnd_ offset
0 1 0 1 bn 7 6 5 4 3 2 1 0
FET Option N P P N Locks EEPROM range: 8140h-817Fh 8120h-813Fh 8100h-811Fh 80C0h-80FFh 8080h-80BFh 8040h-807Fh 8000h-803Fh gnd_offset 100 mV 0 mV
Polarity + - - +
Eliminate offset correction. Shorts 2 x 50 mV sources in current share circuit. Disable groundOK monitor. An open circuit GND pin does not affect VDDOK.
4
b4 0 1
ISHARE_amp_offset 50 mV 0 mV
1
gndok_dis
b1 0 1
GND monitoring enabled. GND monitoring disabled, that is, always OK.
Rev. A | Page 60 of 64
ADM1041 APPENDIX B--TEST NAME TABLE
This table is included for ADI's internal reference use This is a cross reference for the ADI test program. Table 46.
Specification Supplies VDD IDD, Current Consumption Peak IDD, during EEPROM Erase Cycle UNDERVOLTAGE LOCKOUT, VDD Start-Up Threshold Stop Threshold Hysteresis 2.5 V Ref Out Output Voltage Line Regulation Load Regulation Temperature Stability Long-Term Stability Current Limit Output Resistance Load Capacitance Ripple Due to Autozero POWER BLOCK PROTECTION VDD Overvoltage VDD Overvoltage Debounce VREF Overvoltage VREFOUT Undervoltage Open Ground Debounce POWER-ON RESET DC Level DIFFERENTIAL LOAD VOLTAGE SENSE INPUT, (VS-, VS+) VS- Input Voltage VS+ Input Voltage VS- Input Resistance VS+ Input Resistance VNOM Adjustment Range Set Load Voltage Trim Step Minimum Set Load Overvoltage Trim Range Set Load Overvoltage Trim Step Recover from Load OV False to FG True Operate Time from Load OV to FG False LOCAL VOLTAGE SENSE, VLS, AND FALSE UV CLAMP Input Voltage Range Stage Gain False UV Clamp, VLS Input Voltage Nominal, and Trim Range Clamp Trim Step Test Name VDD IDD Specification Local Overvoltage Nominal and Trim Range OV Trim Step, OV Trim Step, Noise Filter, for OVP Function Only Local Undervoltage Nominal and Trim Range UV Trim Step UV Trim Step Noise Filter, for UVP Function Only VOLTAGE ERROR AMPLIFIER Reference Voltage Temperature Coefficient Long-Term Voltage Stability Soft-start Period Range Set Soft-start Period Unity Gain Bandwidth Transconductance Source Current Sink Current DIFFERENTIAL CURRENT SENSE INPUT, CS- CS+ Common-Mode Range, External Divider Tolerance Trim Range (with respect to input) External Divider Tolerance Trim Step Size (with respect to input) DC Offset Trim Range (os_dc_range) (with respect to input) DC Offset Trim Step Size (with respect to input) Total Offset Temperature Drift Gain Range (Isense_range) Gain Setting 1 (16h, B2-0 = 000) Gain Setting 2 (16h, B2-0 = 001) Gain Setting 3 (16h, B2-0 = 010) Gain Setting 4 (16h, B2-0 = 100) Gain Setting 5 (16h, B2-0 = 101) Gain Setting 6 (16h, B2-0 = 110) CURRENT SENSE CALIBRATION Full Scale (No Offset), Attenuation Range Current Share Trim Step (At SHRO), Current Sense Accuracy, (40 mV) Cal. Accuracy, 20 mV at CS+, CS- Cal. Accuracy, 40 mV at CS+, CS- Cal. Accuracy, 40 mV at CS+, CS- Test Name VLSOV VLSOVSTEP VLSOVSTEP TNFOVP VLSUV VLSUVSTEP VLSUVSTEP TNFUVP VCMP VREF_VCMP TCV VSTAB TSSRANGE TSS GBW G mVCMP ISOURCE_VCMP ISINK_VCMP
VDD (ON) VDD (OFF) VDDHYS VREF VREF VLINE VLOAD TCREF VREF_STAB IMAX RO CL VREF_RIPPLE VOVP TDFILTER VRMOVP VROUVP VGND TDEBOUNCE VPOR
VCM_RANGE VOS_DIV_RANGE VOS_DIV_STEP VOS_DC_RANGE VOS_DC_STEP TDRIFT Isense_range G65X G85X G110X G135X G175X G230X VSHR VSHRSTEP TolCSHR TolCSHR TolCSHR
VDVCM VDVIN_MAX VDVINRN VDVINRP VDVADJ VDVTRIM VDVLOV VLOVTRIM TLOADOV_FALSE TLOADOV_TRUE
VLS_RANGE ACLAMP VCLMPTRIM VCLMPSTEP
Rev. A | Page 61 of 64
ADM1041
Specification SHARE BUS OFFSET Current Share Offset Range Zero Current Offset Trim Step CURRENT TRANSFORMER SENSE INPUT Gain Setting 0 Gain Setting 1 CT Input Sensitivity (Gain Set 0) CT Input Sensitivity (Gain Set 1) Input Impedance Source Current Source Current Step Size Reverse Current for Extended SMBus Addressing CURRENT LIMIT ERROR AMPLIFIER Current Limit Trim Range Current Limit Trim Step Current Limit Trim Step Transconductance Output Source Current Output Sink Current CURRENT SHARE DRIVER Output Voltage Short-Circuit Source Current Source Current Sink Current CURRENT SHARE DIFFERENTIAL SENSE AMPLIFIER VS- Input Voltage VSHRS Input Voltage Input Impedance Gain CURRENT SHARE ERROR AMPLIFIER Transconductance, SHRS to SCM Output Source Current Output Sink Current Input Offset Voltage Share OK Window Comparator Threshold (Share Drive Error) CURRENT LIMIT Current Limit Control Lower Threshold Current Limit Control Upper Threshold CURRENT SHARE CAPTURE Current Share Capture Range Capture Threshold FET OR GATE DRIVE Output Low Level (On) Output Leakage Current Polarity Select, Vgateon Test Name VZO VZOSTEP ICT GCT_X4 GCT_X2 VCT_X4 VCT_X2 RIN_CT ISOURCE_CT ISTEP_CT IREV Specification REVERSE VOLTAGE COMPARATOR, FS, FD Common-Mode Range Input Impedance Reverse Voltage Detector Turn-Off Threshold Reverse Voltage Detector Turn-On Threshold ACSENSE1/ACSENSE2 COMPARATOR (AC or Bulk Sense) Threshold Voltage Threshold Adjust Range Threshold Trim Step Hysteresis Voltage Hysteresis Adjust Range Hysteresis Trim Step Noise Filter PULSE-IN Threshold Voltage Pulseok on delay Pulseok off delay OSCILLATOR AND TIMING General Tolerance on Time Delays OCP OCP Threshold Voltage OCP Shutdown Delay Time (Continuous Period in Current Limit) OCP Fast Shutdown Delay Time MON1, MON2, MON3, MON4 Sense Voltage Hysteresis OVP Noise Filter UVP Noise Filter OTP (MON5) Sense Voltage Range OTP Trim Step Hysteresis OVP Noise Filter UVP Noise Filter PSON Input Low Level Input High Level Debounce PEN, DC_OK, CBD, AC_OK Open-Drain N-Channel Option Output Low Level = On Open-Drain P-Channel Output High Level = On Leakage Current Test Name
RFS, RFD VRVD_THRES_OFF VRVD_THRES_ON
CLIM CLIMSTEP CLIMSTEP GmCCMP ISOURCE_CCMP ISINK_CCMP VSHRO_1K ISHRO_SHORT ISHRO_SOURCE ISHRO_SINK
VSNSADJ_THRES VSNSADJ_RANGE VSNSADJ_STEP VSNSHST VSNSHYS_RANGE VSNSHYS_STEP TNFSNS VPULSEMIN TPULSEON TPULSEOFF
VOCP_THRES TOCP_SLOW
TOCP_FAST VMON1 VMON1_HST TNFOVP_MON1 TNFUVP_MON1 VOTP_RANGE VOTP_STEP IOTP_HST TNFOVP_OTP TNFUVP_OTP VIL_PSON VIH_PSON TNF_PSON
RIN_SHR_DIFF GSHR_DIFF GmSCMP ISOURCE_SCMP ISINK_SCMP VIN_SHR_OFF VSHR_THRES
VCLIM_THRES_MIN VCLIM_THRES_MAX
SHRCAPT_RANGE VSHR_CAPT_THRES VLO_FET IOL_FET
VOL_PEN VOH_PEN IOH_PEN
Rev. A | Page 62 of 64
ADM1041
Specification DC_OK DC_OK, On Delay (Power-On and OK Delay) DC_OK, Off Delay (Power-Off Early Warning) SMBus, SDL/SCL Input Voltage Low Input Voltage High Output Voltage Low Pull-Up Current Leakage Current ADD0, HARDWIRED ADDRESS BIT ADD0 Low Level ADD0 Floating ADD0 High Test Name TDCOK_ON TDCOK_OFF Specification SERIAL BUS TIMING Clock Frequency Glitch Immunity Bus Free Time Start Setup Time Start Hold Time SCL Low Time SCL High Time SCL, SDA Rise Time SCL, SDA Fall Time Data Setup Time Data Hold Time EEPROM RELIABILITY Endurance Data Retention Test Name fSCLK tSW tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT
VIL VIH VOL IPULLUP ILEAK
Rev. A | Page 63 of 64
ADM1041 OUTLINE DIMENSIONS
0.341 BSC
24
13
0.154 BSC
1 12
0.236 BSC
PIN 1 0.065 0.049 0.069 0.053
0.010 0.004 COPLANARITY 0.004
0.025 BSC
0.012 0.008
SEATING PLANE
0.010 0.006
8 0
0.050 0.016
COMPLIANT TO JEDEC STANDARDS MO-137AE
Figure 39. 24-Lead QSOP (RQ-24) Dimensions shown in millimeters
ORDERING GUIDE
Model ADM1041ARQ ADM1041ARQ-REEL ADM1041ARQ-REEL7 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 24-Lead QSOP 24-Lead QSOP 24-Lead QSOP Package Option RQ-24 RQ-24 RQ-24
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04521-0-5/04(A)
Rev. A | Page 64 of 64
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